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M6805 Portable Cross Assembler 0.05 MS-DOS/PC-DOS Page 1
Wed May 16 10:07:20 1990
Command line:
C:\BIN\PASM05.EXE -eq -l test1.lst test1.s
Options list:
ON - b - Printing of macro definitions
ON - c - Printing of macro calls
OFF - d - Placing of symbolic debugging information in COFF
ON - e - Printing of macro expansions (changed)
ON - f - Printing of conditional directives
OFF - g - Printing of generated constants list
ON - q - Expanding and printing of structured syntax (changed)
OFF - s - Printing of symbol table
OFF - u - Printing of conditional unassembled source
OFF - x - Printing of cross reference table
OFF - m - Suppress printing of error messages
ON - w - Printing of warning messages
OFF - v - Suppress printing of updated status
OFF - y - Enabling of sgs extensions
ON - o - Create object code
ON - - Formatting of source line listing
Create listing file - l - test1.lst
Xdefs:
NONE
Xrefs:
NONE
Input file(s): test1.s (185 lines)
MACROS05.MAC (2051 lines) RAMSBR.INI (109 lines)
Output file: test1.o
Listing file: test1.lst
M6805 Portable Cross Assembler 0.05 test1.s Page 2
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00002 A 0060 ORG $60 low RAM
00003 * TTL M6805 macro tests: high RAM subr's
00004 * ORG $100 high RAM
00005
00006 A 0060 0000 A ZERO EQU $0
00007 A 0060 0050 A LOW EQU $50
00008 A 0060 0052 A CNTL EQU LOW+2
00009 A 0060 1efc A CNTH EQU $1EFC
00010 A 0060 1efe A HIGH EQU CNTH+2
00011 A 0060 1e00 A HIGH0 EQU $1E00
00012
00013 INCLUDE MACROS05.MAC
M6805 Portable Cross Assembler 0.05 MACROS05.MAC Page 3
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00002 ****************************************************************************
00003 * macros05.mac 1.0
00004 * -------------------------------------------------------------
00005 * Module Name: MACROS05 - M6805 Macros
00006 * -------------------------------------------------------------
00007 *
00008 * Description:
00009 * This file contains macros and subroutines to support pseudo-registers
00010 * on the 6805 that simulate registers and addressing modes available on
00011 * the 68HC11. It is suitable for "black box" operation, i.e., the
00012 * macros may be used without knowledge of how they work. A list of the
00013 * supported macros follows. Consult the individual macro headers for
00014 * usage details and see the "Notes" below.
00015 *
00016 * LDD Load DREG
00017 * STD Store DREG
00018 * ADDD Add DREG
00019 * SUBD Add DREG
00020 * CPD Compare DREG
00021 * LDAXY Load A via 16-bit pseudo-register (XREG or YREG)
00022 * STAXY Store A via 16-bit pseudo-register (XREG or YREG)
00023 * LDXR Load XREG
00024 * STXR Store XREG
00025 * INCXR Increment XREG
00026 * DECXR Decrement XREG
00027 * CPXR Compare XREG
00028 * LDYR Load YREG
00029 * STYR Store YREG
00030 * INCYR Increment YREG
00031 * DECYR Decrement YREG
00032 * CPYR Compare YREG
00033 * DEC.B Decrement byte
00034 * DEC.W Decrement word
00035 * INC.B Increment byte
00036 * INC.W Increment word
00037 * MOV.B Move byte
00038 * MOV.W Move word
00039 * MOVE Move block of memory
00040 *
00041 * General Information:
00042 * The following pseudo-registers are supported.
00043 * DREG = pseudo 16-bit accumulator (A,X registers, A is MS half)
00044 * XREG = pseudo 16-bit index register
00045 * YREG = pseudo 16-bit index register
00046 *
00047 * The following terms are used.
00048 * # = specifies immediate addressing mode
00049 * <address> = address/value operand (absolute or immediate)
00050 * <offset> = unsigned 16-bit offset for indexed addressing
00051 *
00052 * Notes:
M6805 Portable Cross Assembler 0.05 MACROS05.MAC Page 4
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00053 * 1. Motorola reserves the right to make changes to this file.
00054 * Although this file has been carefully reviewed and is believed
00055 * to be reliable, Motorola does not assume any liability arising
00056 * out of its use. This code may be freely used and/or modified at
00057 * no cost or obligation by the user.
00058 * 2. This file was made for use with the Motorola Development Systems
00059 * MC6805 Portable Assembler/Linker for MS-DOS, known as PASM05 and
00060 * PLD, as released on 82HCVBASM B* and 82HCVBLNK B*. Consult the
00061 * PASM and PLD reference manuals, part numbers M68HASM/D1 and
00062 * M68HLINK/D1, for more details.
00063 * 3. These macros were made for ABSOLUTE assemblies only, i.e., for
00064 * use with ORG directives. While most of the macro concepts will
00065 * work in relocatable assemblies (BSCT, DSCT, PSCT, ASCT, XDEF,
00066 * and XREF), errors will be generated because PASM limits the use
00067 * of external symbols in expressions and because the value of an
00068 * expression must be known at assembly time for IFxx directives to
00069 * assemble the proper code. The first restriction is a result of
00070 * limitations in the COFF object file format. If it is desired to
00071 * have these macros work with relocatable assemblies, modifica-
00072 * tions similar to below should be made, but be forewarned of the
00073 * increased inefficiencies in size and speed. Consider the
00074 * following code to change the LDD macro so that an XREF parameter,
00075 * \1, can be loaded as an immediate value.
00076 * LDA \.8
00077 * LDX \.8+1
00078 * BRA \.9
00079 * \.8 FDB \1
00080 * \.9 EQU *
00081 * 4. In order to efficiently support both LOAD and STORE operations
00082 * for the pseudo 16-bit index registers, there are actually two
00083 * such "registers", i.e., one for LOAD and one for STORE as
00084 * defined below. These routines maintain both "registers" with
00085 * the same value, and so the programmer may think of them as one
00086 * register.
00087 * XREG1$ = 16-bit XREG for LOAD operations
00088 * XREG2$ = 16-bit XREG for STORE operations
00089 * YREG1$ = 16-bit YREG for LOAD operations
00090 * YREG2$ = 16-bit YREG for STORE operations
00091 * 5. These macros can be used to create in-line code (speed
00092 * efficient) or they be placed in a subroutine (byte efficient).
00093 * 6. Instruction modified code is used here and is denoted by use
00094 * of the unique string "0-0" (RAM subroutines).
00095 * 7. Some macros use temporary storage locations (TEMPA$, TESTA$,
00096 * etc.), so these macros should not be used in any interrupt
00097 * routine in order to avoid corrupted values!
00098 * 8. The user must ensure that the code is appropriately placed in
00099 * the target M6805's memory map, i.e., the RAM subroutines MUST
00100 * be located in RAM but must not overlap the stack area ($00C0-
00101 * 00FF) unless it can be GUARANTEED there is no conflict! See
00102 * LO$MEM below to set low memory data storage area!
00103 * 9. To use this file, either use an INCLUDE statement or just
00104 * merge this file into your source code file. Consult your
M6805 Portable Cross Assembler 0.05 MACROS05.MAC Page 5
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00105 * assembler's user's manual for the details specific to your
00106 * situation. When using a ROM controlled system, the MOVE
00107 * macro should be used to copy the RAM subroutines from ROM to
00108 * RAM (see the comments after where RAMSBR$ is defined below
00109 * and note the INCLUDE statement for the RAMSBR.INI file).
00110 * Reference the code segment example below for usage ideas
00111 * (shown in PASM05 for MS-DOS syntax).
00112 *
00113 * ORG $50
00114 * TOTAL RMB 2
00115 * RTABLE RMB 5
00116 * INCLUDE MACROS05.MAC
00117 *
00118 * ORG $400
00119 * RESET RSP
00120 * MOVE #,.RAMSBR$,#,RAMSBR$,#,RAMSZ$ Init ram.
00121 * START MOV.W #,0,TOTAL
00122 * LDD COST
00123 * ADDD #,1000
00124 * SUBD #,ADJUST
00125 * ADDD TOTAL
00126 * STDD TOTAL
00127 * CPD #,1500
00128 * BEQ MATCH
00129 * *
00130 * LDXR #,0
00131 * LDYR #,0
00132 * LOOP LDAXY TABLE,XREG
00133 * STAXY RTABLE,YREG
00134 * INCXR
00135 * INCYR
00136 * CPY #,5
00137 * BNE LOOP
00138 * .
00139 * .
00140 * INCLUDE RAMSBR.INI
00141 * TABLE FCB 1,2,3,4,5
00142 * ADJUST FDB 150
00143 * COST FDB 859
00144 * .
00145 * .
00146 * END
00147 *
00148 * 10. To assemble, use the following sample invocation lines:
00149 * pasm05 -eq -l filename.lst filename.s (debug= expanded)
00150 * or
00151 * pasm05 -bf -l filename.lst filename.s (black box)
00152 * 11. Notations used by PASM05 are as follows:
00153 * OPERATORS: Special two character operators used are...
00154 * 1. Logical AND !.
00155 * 2. Shift Right (0 fill on left) !>
00156 * MACROS: Special notations used are...
M6805 Portable Cross Assembler 0.05 MACROS05.MAC Page 6
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00157 * 1. Parameters are positionally named using \0,
00158 * \1, \2, etc.
00159 * 2. Labels within macros are designated via \.a,
00160 * where "a" is an alphanumeric character. The
00161 * assembler generates a unique label to avoid
00162 * multiply defined label problems.
00163 * 12. Some macros access 16-bit values as LS byte then MS byte in order
00164 * to be more efficient for condition code (CC) setting. This is
00165 * the reverse order that the 68HC11 would access the two byte
00166 * halves. This difference would only be a concern in accessing
00167 * hardware registers, as normal RAM makes no difference. Those
00168 * macros with this difference have an entry in their Notes section.
00169 * 13. The latest version of this file is maintained on the Motorola
00170 * FREEWARE Bulletin Board, 512/891-FREE (512/891-3733). It operates
00171 * continuously (except for maintenance) at 1200-2400 baud, 8 bits,
00172 * no parity. Sample test files for PASM05 are also included.
00173 * Download the archive file, MACROS05.ARC, to get all the files.
00174 *
00175 **************************************************************************
00176 * REVISION HISTORY (add new changes to top):
00177 *
00178 * 05/16/90 P.S. Gilmour
00179 * 1. Created for Application Note AN1055.
00180 **************************************************************************
00181 A 0060 00b9 A LO$MEM EQU $00C0-7 Low memory ($0000-00FF) storage (7 bytes)
00182
00183 OPT NOL
01963 OPT L
01964 A 0060 0060 A RAMSBR$ EQU * Start of RAM based subroutines!
01965 **************************************************************************
01966 ** The following RAM subroutines MUST BE INITIALIZED from ROM upon **
01967 ** startup (from 'RAMSBR$' for 'RAMSZ$' number of bytes). If changes **
01968 ** are to be made to the RAM subroutines, make them here. Then copy **
01969 ** the source below to the ROM area and insert a '.' in front of all **
01970 ** the labels (leading '.' will be used to denote ROM). This has **
01971 ** already been done for you in the RAMSBR.INI file. Just include **
01972 ** this file into your ROM data area and add the following line in **
01973 ** your RESET routine to initialize the RAM subroutines from the ROM. **
01974 ** MOVE #,.RAMSBR,#,RAMSBR,#,RAMSZ$ **
01975 ** It is more efficient if the RAM subroutines are placed in DIRECT **
01976 ** addressing memory, i.e., $0000-$00FF, but it is not required. **
01977 **************************************************************************
01978
01979 *-- start of RAM subroutines --------------------------------------------*
01980 **************************************************************************
01981 * LDAXREG = load A via XREG subr.
01982 *
01983 * Register Usage:
01984 * CC = reflects value loaded.
01985 * All other registers preserved.
01986 *
01987 * NOTE:
M6805 Portable Cross Assembler 0.05 MACROS05.MAC Page 7
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
01988 * 1. Instruction modified code here must be located in RAM!
01989 *
01990 A 0060 0060 A LDAXREG EQU *
01991 A 0060 c6 ffff A LDA 0-0+$FFFF
01992 A 0063 0061 A XREG1$ EQU *-2 Pseudo XREG #1
01993 A 0063 81 RTS
01994
01995 **************************************************************************
01996 * STAXREG = store A via XREG subr.
01997 *
01998 * Register Usage:
01999 * CC = reflects value stored.
02000 * All other registers preserved.
02001 *
02002 * NOTE:
02003 * 1. Instruction modified code here must be located in RAM!
02004 *
02005 A 0064 0064 A STAXREG EQU *
02006 A 0064 c7 ffff A STA 0-0+$FFFF
02007 A 0067 0065 A XREG2$ EQU *-2 Pseudo XREG #2
02008 A 0067 81 RTS
02009
02010 **************************************************************************
02011 * LDAYREG = load A via YREG subr.
02012 *
02013 * Register Usage:
02014 * CC = reflects value loaded.
02015 * All other registers preserved.
02016 *
02017 * NOTE:
02018 * 1. Instruction modified code here must be located in RAM!
02019 *
02020 A 0068 0068 A LDAYREG EQU *
02021 A 0068 c6 ffff A LDA 0-0+$FFFF
02022 A 006b 0069 A YREG1$ EQU *-2 Pseudo YREG #1
02023 A 006b 81 RTS
02024
02025 **************************************************************************
02026 * STAYREG = store A via YREG subr.
02027 *
02028 * Register Usage:
02029 * CC = reflects value stored.
02030 * All other registers preserved.
02031 *
02032 * NOTE:
02033 * 1. Instruction modified code here must be located in RAM!
02034 *
02035 A 006c 006c A STAYREG EQU *
02036 A 006c c7 ffff A STA 0-0+$FFFF
02037 A 006f 006d A YREG2$ EQU *-2 Pseudo YREG #2
02038 A 006f 81 RTS
02039 *-- end of RAM subroutines ----------------------------------------------*
M6805 Portable Cross Assembler 0.05 MACROS05.MAC Page 8
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
02040
02041 A 0070 0010 A RAMSZ$ EQU *-RAMSBR$ Size of ram subroutines (in bytes).
02042
02043 A 00b9 ORG LO$MEM
02044 * NOTE: TEMPA$ and TESTA$ must always be in low memory $0000-00FF.
02045 A 00b9 01 A TEMPA$ RMB 1 Temporary storage for A accumulator.
02046 A 00ba 01 A TEMPX$ RMB 1 Temporary storage for X register.
02047 A 00bb 02 A TEMPXR$ RMB 2 Temporary storage for XREG register.
02048 A 00bd 01 A TESTA$ RMB 1 Temporary operand storage for setting CC bits.
02049 A 00be 02 A LENGTH$ RMB 2 Temporary operand length.
02050
02051 **************************************************************************
00014
00015 A 0400 ORG $400
00016 INCLUDE RAMSBR.INI
00001
00002 ****************************************************************************
00003 * ramsbr.ini 1.0
00004 * -------------------------------------------------------------
00005 * Module Name: RAMSBR - RAM Subroutine Initialization
00006 * -------------------------------------------------------------
00007 *
00008 * Description:
00009 * This file contains the initialization code for the RAM subroutine
00010 * area needed to support the MACROS05.MAC file. It MUST be placed in
00011 * the ROM data area and then copied to RAM for proper operation.
00012 * Consult the MACROS05.MAC file for more details.
00013 *
00014 ****************************************************************************
00015 *
00016 * Notes:
00017 * 1. Motorola reserves the right to make changes to this file.
00018 * Although this file has been carefully reviewed and is
00019 * believed to be reliable, Motorola does not assume any
00020 * liability arising out of its use. This code may be freely
00021 * used and/or modified at no cost or obligation by the user.
00022 * 2. The latest version of this file is maintained on the Motorola
00023 * FREEWARE Bulletin Board, 512/891-FREE (512/891-3733). It operates
00024 * continuously (except for maintenance) at 1200-2400 baud, 8 bits,
00025 * no parity. Sample test files for PASM05 are also included.
00026 * Download the archive file, MACROS05.ARC, to get all the files.
00027 *
00028 **************************************************************************
00029 * REVISION HISTORY (add new changes to top):
00030 *
00031 * 05/16/90 P.S. Gilmour
00032 * 1. Original entry generated from MACROS05.MAC version 1.0.
00033 ****************************************************************************
00034
00035 A 0400 0400 A .RAMSBR$ EQU * Start of RAM based subroutines!
00036 **************************************************************************
00037 ** The following RAM subroutines MUST BE INITIALIZED from ROM upon **
M6805 Portable Cross Assembler 0.05 RAMSBR.INI Page 9
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00038 ** startup (from 'RAMSBR$' for 'RAMSZ$' number of bytes). If changes **
00039 ** are to be made to the RAM subroutines, make them in the MACROS05.MAC**
00040 ** file and then copy the source here (ROM area) and insert a '.' in **
00041 ** front of all the labels (leading '.' will be used to denote ROM). **
00042 **************************************************************************
00043
00044 *-- start of RAM subroutines --------------------------------------------*
00045 **************************************************************************
00046 * LDAXREG = load A via XREG subr.
00047 *
00048 * Register Usage:
00049 * CC = reflects value loaded.
00050 * All other registers preserved.
00051 *
00052 * NOTE:
00053 * 1. Instruction modified code here must be located in RAM!
00054 *
00055 A 0400 0400 A .LDAXREG EQU *
00056 A 0400 c6 ffff A LDA 0-0+$FFFF
00057 A 0403 0401 A .XREG1$ EQU *-2 Pseudo XREG #1
00058 A 0403 81 RTS
00059
00060 **************************************************************************
00061 * STA$X = store A via XREG subr.
00062 *
00063 * Register Usage:
00064 * CC = reflects value stored.
00065 * All other registers preserved.
00066 *
00067 * NOTE:
00068 * 1. Instruction modified code here must be located in RAM!
00069 *
00070 A 0404 0404 A .STA$X EQU *
00071 A 0404 c7 ffff A STA 0-0+$FFFF
00072 A 0407 0405 A .XREG2$ EQU *-2 Pseudo XREG #2
00073 A 0407 81 RTS
00074
00075 **************************************************************************
00076 * LDAYREG = load A via YREG subr.
00077 *
00078 * Register Usage:
00079 * CC = reflects value loaded.
00080 * All other registers preserved.
00081 *
00082 * NOTE:
00083 * 1. Instruction modified code here must be located in RAM!
00084 *
00085 A 0408 0408 A .LDAYREG EQU *
00086 A 0408 c6 ffff A LDA 0-0+$FFFF
00087 A 040b 0409 A .YREG1$ EQU *-2 Pseudo YREG #1
00088 A 040b 81 RTS
00089
M6805 Portable Cross Assembler 0.05 RAMSBR.INI Page 10
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00090 **************************************************************************
00091 * STA$Y = store A via YREG subr.
00092 *
00093 * Register Usage:
00094 * CC = reflects value stored.
00095 * All other registers preserved.
00096 *
00097 * NOTE:
00098 * 1. Instruction modified code here must be located in RAM!
00099 *
00100 A 040c 040c A .STA$Y EQU *
00101 A 040c c7 ffff A STA 0-0+$FFFF
00102 A 040f 040d A .YREG2$ EQU *-2 Pseudo YREG #2
00103 A 040f 81 RTS
00104 *-- end of RAM subroutines ----------------------------------------------*
00105
00106 A 0410 0010 A .RAMSZ$ EQU *-.RAMSBR$ Size of ram subroutines (in bytes).
00107 IFNE RAMSZ$-.RAMSZ$
00109 ENDC
00017
00018 A 0410 0410 A START EQU *
00019 * @@@@@@@@ DREG tests start here
00020 MACRO INV LDD ZERO !-------------------------
00020 + IFEQ NARG-1
00020 +A 0410 be 01 A LDX (ZERO)+1
00020 +A 0412 b6 00 A LDA (ZERO)
00021 MACRO INV LDD LOW !-------------------------
00021 + IFEQ NARG-1
00021 +A 0414 be 51 A LDX (LOW)+1
00021 +A 0416 b6 50 A LDA (LOW)
00022 MACRO INV LDD HIGH !-------------------------
00022 + IFEQ NARG-1
00022 +A 0418 ce 1eff A LDX (HIGH)+1
00022 +A 041b c6 1efe A LDA (HIGH)
00023 MACRO INV LDD #,0 !-------------------------
00023 + IFEQ NARG-1
00023 + ENDC
00023 + IFEQ NARG-2
00023 + IFC '#','#'
00023 + IFEQ (0)!.$FF
00023 +A 041e 5f CLRX
00023 + ENDC
00023 + IFNE (0)!.$FF
00023 + ENDC
00023 + IFEQ (0)!>8
00023 +A 041f 4f CLRA
00023 + ENDC
00023 + IFNE (0)!>8
00023 + ENDC
00024 MACRO INV LDD #,LOW !-------------------------
00024 + IFEQ NARG-1
00024 + ENDC
M6805 Portable Cross Assembler 0.05 test1.s Page 11
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00024 + IFEQ NARG-2
00024 + IFC '#','#'
00024 + IFEQ (LOW)!.$FF
00024 + ENDC
00024 + IFNE (LOW)!.$FF
00024 +A 0420 ae 50 A LDX #(LOW)!.$FF
00024 + ENDC
00024 + IFEQ (LOW)!>8
00024 +A 0422 4f CLRA
00024 + ENDC
00024 + IFNE (LOW)!>8
00024 + ENDC
00025 MACRO INV LDD #,HIGH !-------------------------
00025 + IFEQ NARG-1
00025 + ENDC
00025 + IFEQ NARG-2
00025 + IFC '#','#'
00025 + IFEQ (HIGH)!.$FF
00025 + ENDC
00025 + IFNE (HIGH)!.$FF
00025 +A 0423 ae fe A LDX #(HIGH)!.$FF
00025 + ENDC
00025 + IFEQ (HIGH)!>8
00025 + ENDC
00025 + IFNE (HIGH)!>8
00025 +A 0425 a6 1e A LDA #(HIGH)!>8
00025 + ENDC
00026 MACRO INV LDD #,HIGH0 !-------------------------
00026 + IFEQ NARG-1
00026 + ENDC
00026 + IFEQ NARG-2
00026 + IFC '#','#'
00026 + IFEQ (HIGH0)!.$FF
00026 +A 0427 5f CLRX
00026 + ENDC
00026 + IFNE (HIGH0)!.$FF
00026 + ENDC
00026 + IFEQ (HIGH0)!>8
00026 + ENDC
00026 + IFNE (HIGH0)!>8
00026 +A 0428 a6 1e A LDA #(HIGH0)!>8
00026 + ENDC
00027 MACRO INV STD LOW !-------------------------
00027 +A 042a bf 51 A STX (LOW)+1
00027 +A 042c b7 50 A STA (LOW)
00027 +
00028 MACRO INV STD HIGH !-------------------------
00028 +A 042e cf 1eff A STX (HIGH)+1
00028 +A 0431 c7 1efe A STA (HIGH)
00028 +
00029
00030 MACRO INV ADDD LOW !-------------------------
M6805 Portable Cross Assembler 0.05 test1.s Page 12
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00030 + IFEQ NARG-1
00030 +A 0434 b7 b9 A STA TEMPA$
00030 +A 0436 9f TXA
00030 +A 0437 bb 51 A ADD (LOW)+1
00030 +A 0439 97 TAX
00030 +A 043a b6 b9 A LDA TEMPA$
00030 +A 043c b9 50 A ADC (LOW)
00031 MACRO INV ADDD HIGH !-------------------------
00031 + IFEQ NARG-1
00031 +A 043e b7 b9 A STA TEMPA$
00031 +A 0440 9f TXA
00031 +A 0441 cb 1eff A ADD (HIGH)+1
00031 +A 0444 97 TAX
00031 +A 0445 b6 b9 A LDA TEMPA$
00031 +A 0447 c9 1efe A ADC (HIGH)
00032 MACRO INV ADDD #,LOW !-------------------------
00032 + IFEQ NARG-1
00032 + ENDC
00032 + IFEQ NARG-2
00032 + IFC '#','#'
00032 +A 044a b7 b9 A STA TEMPA$
00032 +A 044c 9f TXA
00032 +A 044d ab 50 A ADD #(LOW)!.$FF
00032 +A 044f 97 TAX
00032 +A 0450 b6 b9 A LDA TEMPA$
00032 +A 0452 a9 00 A ADC #(LOW)!>8
00033 MACRO INV ADDD #,HIGH !-------------------------
00033 + IFEQ NARG-1
00033 + ENDC
00033 + IFEQ NARG-2
00033 + IFC '#','#'
00033 +A 0454 b7 b9 A STA TEMPA$
00033 +A 0456 9f TXA
00033 +A 0457 ab fe A ADD #(HIGH)!.$FF
00033 +A 0459 97 TAX
00033 +A 045a b6 b9 A LDA TEMPA$
00033 +A 045c a9 1e A ADC #(HIGH)!>8
00034
00035 MACRO INV SUBD LOW !-------------------------
00035 + IFEQ NARG-1
00035 +A 045e b7 b9 A STA TEMPA$
00035 +A 0460 9f TXA
00035 +A 0461 b0 51 A SUB (LOW)+1
00035 +A 0463 97 TAX
00035 +A 0464 b6 b9 A LDA TEMPA$
00035 +A 0466 b2 50 A SBC (LOW)
00036 MACRO INV SUBD HIGH !-------------------------
00036 + IFEQ NARG-1
00036 +A 0468 b7 b9 A STA TEMPA$
00036 +A 046a 9f TXA
00036 +A 046b c0 1eff A SUB (HIGH)+1
00036 +A 046e 97 TAX
M6805 Portable Cross Assembler 0.05 test1.s Page 13
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00036 +A 046f b6 b9 A LDA TEMPA$
00036 +A 0471 c2 1efe A SBC (HIGH)
00037 MACRO INV SUBD #,LOW !-------------------------
00037 + IFEQ NARG-1
00037 + ENDC
00037 + IFEQ NARG-2
00037 + IFC '#','#'
00037 +A 0474 b7 b9 A STA TEMPA$
00037 +A 0476 9f TXA
00037 +A 0477 a0 50 A SUB #(LOW)!.$FF
00037 +A 0479 97 TAX
00037 +A 047a b6 b9 A LDA TEMPA$
00037 +A 047c a2 00 A SBC #(LOW)!>8
00038 MACRO INV SUBD #,HIGH !-------------------------
00038 + IFEQ NARG-1
00038 + ENDC
00038 + IFEQ NARG-2
00038 + IFC '#','#'
00038 +A 047e b7 b9 A STA TEMPA$
00038 +A 0480 9f TXA
00038 +A 0481 a0 fe A SUB #(HIGH)!.$FF
00038 +A 0483 97 TAX
00038 +A 0484 b6 b9 A LDA TEMPA$
00038 +A 0486 a2 1e A SBC #(HIGH)!>8
00039
00040 MACRO INV CPD ZERO !-------------------------
00040 + IFEQ NARG-1
00040 +A 0488 b3 01 A CPX (ZERO)+1
00040 +A 048a 26 02 048e BNE .00017
00040 +A 048c b1 00 A CMP (ZERO)
00040 +A 048e 048e A .00017 EQU *
00041 MACRO INV CPD LOW !-------------------------
00041 + IFEQ NARG-1
00041 +A 048e b3 51 A CPX (LOW)+1
00041 +A 0490 26 02 0494 BNE .00018
00041 +A 0492 b1 50 A CMP (LOW)
00041 +A 0494 0494 A .00018 EQU *
00042 MACRO INV CPD HIGH !-------------------------
00042 + IFEQ NARG-1
00042 +A 0494 c3 1eff A CPX (HIGH)+1
00042 +A 0497 26 03 049c BNE .00019
00042 +A 0499 c1 1efe A CMP (HIGH)
00042 +A 049c 049c A .00019 EQU *
00043 MACRO INV CPD #,0 !-------------------------
00043 + IFEQ NARG-1
00043 + ENDC
00043 + IFEQ NARG-2
00043 + IFC '#','#'
00043 + IFEQ (0)!.$FF
00043 +A 049c 5d TSTX
00043 + ENDC
00043 + IFNE (0)!.$FF
M6805 Portable Cross Assembler 0.05 test1.s Page 14
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00043 + ENDC
00043 +A 049d 26 01 04a0 BNE .00020
00043 + IFEQ (0)!>8
00043 +A 049f 4d TSTA
00043 + ENDC
00043 + IFNE (0)!>8
00043 + ENDC
00043 +A 04a0 04a0 A .00020 EQU *
00044 MACRO INV CPD #,LOW !-------------------------
00044 + IFEQ NARG-1
00044 + ENDC
00044 + IFEQ NARG-2
00044 + IFC '#','#'
00044 + IFEQ (LOW)!.$FF
00044 + ENDC
00044 + IFNE (LOW)!.$FF
00044 +A 04a0 a3 50 A CPX #(LOW)!.$FF
00044 + ENDC
00044 +A 04a2 26 01 04a5 BNE .00021
00044 + IFEQ (LOW)!>8
00044 +A 04a4 4d TSTA
00044 + ENDC
00044 + IFNE (LOW)!>8
00044 + ENDC
00044 +A 04a5 04a5 A .00021 EQU *
00045 MACRO INV CPD #,HIGH !-------------------------
00045 + IFEQ NARG-1
00045 + ENDC
00045 + IFEQ NARG-2
00045 + IFC '#','#'
00045 + IFEQ (HIGH)!.$FF
00045 + ENDC
00045 + IFNE (HIGH)!.$FF
00045 +A 04a5 a3 fe A CPX #(HIGH)!.$FF
00045 + ENDC
00045 +A 04a7 26 02 04ab BNE .00022
00045 + IFEQ (HIGH)!>8
00045 + ENDC
00045 + IFNE (HIGH)!>8
00045 +A 04a9 a1 1e A CMP #(HIGH)!>8
00045 + ENDC
00045 +A 04ab 04ab A .00022 EQU *
00046 MACRO INV CPD #,HIGH0 !-------------------------
00046 + IFEQ NARG-1
00046 + ENDC
00046 + IFEQ NARG-2
00046 + IFC '#','#'
00046 + IFEQ (HIGH0)!.$FF
00046 +A 04ab 5d TSTX
00046 + ENDC
00046 + IFNE (HIGH0)!.$FF
00046 + ENDC
M6805 Portable Cross Assembler 0.05 test1.s Page 15
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00046 +A 04ac 26 02 04b0 BNE .00023
00046 + IFEQ (HIGH0)!>8
00046 + ENDC
00046 + IFNE (HIGH0)!>8
00046 +A 04ae a1 1e A CMP #(HIGH0)!>8
00046 + ENDC
00046 +A 04b0 04b0 A .00023 EQU *
00047
00048 * @@@@@@@@ XREG tests start here
00049 MACRO INV LDAXY ,XREG !-------------------------
00049 + IFNC 'XREG','XREG'
00049 + ENDC
00049 + IFC '',''
00049 +A 04b0 bd 60 A JSR LDAXREG Default offset= 0
00050 MACRO INV LDAXY 0,XREG !-------------------------
00050 + IFNC 'XREG','XREG'
00050 + ENDC
00050 + IFC '0',''
00050 + ENDC
00050 + IFNC '0',''
00050 + IFEQ 0
00050 +A 04b2 bd 60 A JSR LDAXREG Offset= 0
00051 MACRO INV LDAXY 5,XREG !-------------------------
00051 + IFNC 'XREG','XREG'
00051 + ENDC
00051 + IFC '5',''
00051 + ENDC
00051 + IFNC '5',''
00051 + IFEQ 5
00051 + ENDC
00051 + IFNE 5
00051 +A 04b4 b6 62 A LDA XREG1$+1 Set nREG= offset + nREG
00051 +A 04b6 ab 05 A ADD #(5)!.$FF
00051 +A 04b8 b7 62 A STA XREG1$+1
00051 +A 04ba b6 61 A LDA XREG1$
00051 +A 04bc a9 00 A ADC #(5)!>8
00051 +A 04be b7 61 A STA XREG1$
00051 +A 04c0 bd 60 A JSR LDAXREG Offset= 0
00051 +A 04c2 b7 b9 A STA TEMPA$
00051 +A 04c4 b6 65 A LDA XREG2$ Restore nREG
00051 +A 04c6 b7 61 A STA XREG1$
00051 +A 04c8 b6 66 A LDA XREG2$+1
00051 +A 04ca b7 62 A STA XREG1$+1
00051 +A 04cc b6 b9 A LDA TEMPA$
00052 MACRO INV LDAXY LOW,XREG !------------------------
00052 + IFNC 'XREG','XREG'
00052 + ENDC
00052 + IFC 'LOW',''
00052 + ENDC
00052 + IFNC 'LOW',''
00052 + IFEQ LOW
00052 + ENDC
M6805 Portable Cross Assembler 0.05 test1.s Page 16
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00052 + IFNE LOW
00052 +A 04ce b6 62 A LDA XREG1$+1 Set nREG= offset + nREG
00052 +A 04d0 ab 50 A ADD #(LOW)!.$FF
00052 +A 04d2 b7 62 A STA XREG1$+1
00052 +A 04d4 b6 61 A LDA XREG1$
00052 +A 04d6 a9 00 A ADC #(LOW)!>8
00052 +A 04d8 b7 61 A STA XREG1$
00052 +A 04da bd 60 A JSR LDAXREG Offset= 0
00052 +A 04dc b7 b9 A STA TEMPA$
00052 +A 04de b6 65 A LDA XREG2$ Restore nREG
00052 +A 04e0 b7 61 A STA XREG1$
00052 +A 04e2 b6 66 A LDA XREG2$+1
00052 +A 04e4 b7 62 A STA XREG1$+1
00052 +A 04e6 b6 b9 A LDA TEMPA$
00053 MACRO INV LDAXY HIGH,XREG !-----------------------
00053 + IFNC 'XREG','XREG'
00053 + ENDC
00053 + IFC 'HIGH',''
00053 + ENDC
00053 + IFNC 'HIGH',''
00053 + IFEQ HIGH
00053 + ENDC
00053 + IFNE HIGH
00053 +A 04e8 b6 62 A LDA XREG1$+1 Set nREG= offset + nREG
00053 +A 04ea ab fe A ADD #(HIGH)!.$FF
00053 +A 04ec b7 62 A STA XREG1$+1
00053 +A 04ee b6 61 A LDA XREG1$
00053 +A 04f0 a9 1e A ADC #(HIGH)!>8
00053 +A 04f2 b7 61 A STA XREG1$
00053 +A 04f4 bd 60 A JSR LDAXREG Offset= 0
00053 +A 04f6 b7 b9 A STA TEMPA$
00053 +A 04f8 b6 65 A LDA XREG2$ Restore nREG
00053 +A 04fa b7 61 A STA XREG1$
00053 +A 04fc b6 66 A LDA XREG2$+1
00053 +A 04fe b7 62 A STA XREG1$+1
00053 +A 0500 b6 b9 A LDA TEMPA$
00054
00055 MACRO INV STAXY ,XREG !-------------------------
00055 + IFNC 'XREG','XREG'
00055 + ENDC
00055 + IFC '',''
00055 +A 0502 bd 64 A JSR STAXREG Default offset= 0
00056 MACRO INV STAXY 0,XREG !-------------------------
00056 + IFNC 'XREG','XREG'
00056 + ENDC
00056 + IFC '0',''
00056 + ENDC
00056 + IFNC '0',''
00056 + IFEQ 0
00056 +A 0504 bd 64 A JSR STAXREG Offset= 0
00057 MACRO INV STAXY 5,XREG !-------------------------
00057 + IFNC 'XREG','XREG'
M6805 Portable Cross Assembler 0.05 test1.s Page 17
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00057 + ENDC
00057 + IFC '5',''
00057 + ENDC
00057 + IFNC '5',''
00057 + IFEQ 5
00057 + ENDC
00057 + IFNE 5
00057 +A 0506 b7 b9 A STA TEMPA$
00057 +A 0508 b6 66 A LDA XREG2$+1 Set nREG= offset + nREG
00057 +A 050a ab 05 A ADD #(5)!.$FF
00057 +A 050c b7 66 A STA XREG2$+1
00057 +A 050e b6 65 A LDA XREG2$
00057 +A 0510 a9 00 A ADC #(5)!>8
00057 +A 0512 b7 65 A STA XREG2$
00057 +A 0514 b6 b9 A LDA TEMPA$
00057 +A 0516 bd 64 A JSR STAXREG Offset= 0
00057 +A 0518 b6 61 A LDA XREG1$ Restore nREG
00057 +A 051a b7 65 A STA XREG2$
00057 +A 051c b6 62 A LDA XREG1$+1
00057 +A 051e b7 66 A STA XREG2$+1
00057 +A 0520 b6 b9 A LDA TEMPA$
00058 MACRO INV STAXY LOW,XREG !------------------------
00058 + IFNC 'XREG','XREG'
00058 + ENDC
00058 + IFC 'LOW',''
00058 + ENDC
00058 + IFNC 'LOW',''
00058 + IFEQ LOW
00058 + ENDC
00058 + IFNE LOW
00058 +A 0522 b7 b9 A STA TEMPA$
00058 +A 0524 b6 66 A LDA XREG2$+1 Set nREG= offset + nREG
00058 +A 0526 ab 50 A ADD #(LOW)!.$FF
00058 +A 0528 b7 66 A STA XREG2$+1
00058 +A 052a b6 65 A LDA XREG2$
00058 +A 052c a9 00 A ADC #(LOW)!>8
00058 +A 052e b7 65 A STA XREG2$
00058 +A 0530 b6 b9 A LDA TEMPA$
00058 +A 0532 bd 64 A JSR STAXREG Offset= 0
00058 +A 0534 b6 61 A LDA XREG1$ Restore nREG
00058 +A 0536 b7 65 A STA XREG2$
00058 +A 0538 b6 62 A LDA XREG1$+1
00058 +A 053a b7 66 A STA XREG2$+1
00058 +A 053c b6 b9 A LDA TEMPA$
00059 MACRO INV STAXY HIGH,XREG !-----------------------
00059 + IFNC 'XREG','XREG'
00059 + ENDC
00059 + IFC 'HIGH',''
00059 + ENDC
00059 + IFNC 'HIGH',''
00059 + IFEQ HIGH
00059 + ENDC
M6805 Portable Cross Assembler 0.05 test1.s Page 18
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00059 + IFNE HIGH
00059 +A 053e b7 b9 A STA TEMPA$
00059 +A 0540 b6 66 A LDA XREG2$+1 Set nREG= offset + nREG
00059 +A 0542 ab fe A ADD #(HIGH)!.$FF
00059 +A 0544 b7 66 A STA XREG2$+1
00059 +A 0546 b6 65 A LDA XREG2$
00059 +A 0548 a9 1e A ADC #(HIGH)!>8
00059 +A 054a b7 65 A STA XREG2$
00059 +A 054c b6 b9 A LDA TEMPA$
00059 +A 054e bd 64 A JSR STAXREG Offset= 0
00059 +A 0550 b6 61 A LDA XREG1$ Restore nREG
00059 +A 0552 b7 65 A STA XREG2$
00059 +A 0554 b6 62 A LDA XREG1$+1
00059 +A 0556 b7 66 A STA XREG2$+1
00059 +A 0558 b6 b9 A LDA TEMPA$
00060
00061 MACRO INV LDXR ZERO !-------------------------
00061 + IFEQ NARG-1
00061 +A 055a b7 b9 A STA TEMPA$
00061 +A 055c b6 01 A LDA (ZERO)+1
00061 +A 055e b7 62 A STA XREG1$+1
00061 +A 0560 b7 66 A STA XREG2$+1
00061 +A 0562 b6 00 A LDA (ZERO)
00061 +A 0564 b7 61 A STA XREG1$
00061 +A 0566 b7 65 A STA XREG2$
00061 + IFEQ XREG1$!.$FF00
00061 +A 0568 b6 b9 A LDA TEMPA$
00061 +A 056a 3d 61 A TST XREG1$
00061 + ENDC
00061 + IFNE XREG1$!.$FF00
00061 + ENDC
00062 MACRO INV LDXR LOW !-------------------------
00062 + IFEQ NARG-1
00062 +A 056c b7 b9 A STA TEMPA$
00062 +A 056e b6 51 A LDA (LOW)+1
00062 +A 0570 b7 62 A STA XREG1$+1
00062 +A 0572 b7 66 A STA XREG2$+1
00062 +A 0574 b6 50 A LDA (LOW)
00062 +A 0576 b7 61 A STA XREG1$
00062 +A 0578 b7 65 A STA XREG2$
00062 + IFEQ XREG1$!.$FF00
00062 +A 057a b6 b9 A LDA TEMPA$
00062 +A 057c 3d 61 A TST XREG1$
00062 + ENDC
00062 + IFNE XREG1$!.$FF00
00062 + ENDC
00063 MACRO INV LDXR HIGH !-------------------------
00063 + IFEQ NARG-1
00063 +A 057e b7 b9 A STA TEMPA$
00063 +A 0580 c6 1eff A LDA (HIGH)+1
00063 +A 0583 b7 62 A STA XREG1$+1
00063 +A 0585 b7 66 A STA XREG2$+1
M6805 Portable Cross Assembler 0.05 test1.s Page 19
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00063 +A 0587 c6 1efe A LDA (HIGH)
00063 +A 058a b7 61 A STA XREG1$
00063 +A 058c b7 65 A STA XREG2$
00063 + IFEQ XREG1$!.$FF00
00063 +A 058e b6 b9 A LDA TEMPA$
00063 +A 0590 3d 61 A TST XREG1$
00063 + ENDC
00063 + IFNE XREG1$!.$FF00
00063 + ENDC
00064 MACRO INV LDXR #,0 !-------------------------
00064 + IFEQ NARG-1
00064 + ENDC
00064 + IFEQ NARG-2
00064 + IFC '#','#'
00064 + IFEQ XREG1$!.$FF00 ! XREG in low memory?
00064 + IFEQ 0 ! #0 value?
00064 +A 0592 3f 62 A CLR XREG1$+1
00064 +A 0594 3f 66 A CLR XREG2$+1
00064 +A 0596 3f 61 A CLR XREG1$
00064 +A 0598 3f 65 A CLR XREG2$
00065 MACRO INV LDXR #,LOW !-------------------------
00065 + IFEQ NARG-1
00065 + ENDC
00065 + IFEQ NARG-2
00065 + IFC '#','#'
00065 + IFEQ XREG1$!.$FF00 ! XREG in low memory?
00065 + IFEQ LOW ! #0 value?
00065 + ENDC
00065 + IFNE LOW ! not #0 value?
00065 +A 059a b7 b9 A STA TEMPA$
00065 + IFEQ (LOW)!.$FF
00065 + ENDC
00065 + IFNE (LOW)!.$FF
00065 +A 059c a6 50 A LDA #(LOW)!.$FF
00065 +A 059e b7 62 A STA XREG1$+1
00065 +A 05a0 b7 66 A STA XREG2$+1
00065 + ENDC
00065 + IFEQ (LOW)!>8
00065 +A 05a2 3f 61 A CLR XREG1$
00065 +A 05a4 3f 65 A CLR XREG2$
00065 + ENDC
00065 + IFNE (LOW)!>8
00065 + ENDC
00065 +A 05a6 b6 b9 A LDA TEMPA$
00065 +A 05a8 3d 61 A TST XREG1$
00066 MACRO INV LDXR #,HIGH !-------------------------
00066 + IFEQ NARG-1
00066 + ENDC
00066 + IFEQ NARG-2
00066 + IFC '#','#'
00066 + IFEQ XREG1$!.$FF00 ! XREG in low memory?
00066 + IFEQ HIGH ! #0 value?
M6805 Portable Cross Assembler 0.05 test1.s Page 20
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00066 + ENDC
00066 + IFNE HIGH ! not #0 value?
00066 +A 05aa b7 b9 A STA TEMPA$
00066 + IFEQ (HIGH)!.$FF
00066 + ENDC
00066 + IFNE (HIGH)!.$FF
00066 +A 05ac a6 fe A LDA #(HIGH)!.$FF
00066 +A 05ae b7 62 A STA XREG1$+1
00066 +A 05b0 b7 66 A STA XREG2$+1
00066 + ENDC
00066 + IFEQ (HIGH)!>8
00066 + ENDC
00066 + IFNE (HIGH)!>8
00066 +A 05b2 a6 1e A LDA #(HIGH)!>8
00066 +A 05b4 b7 61 A STA XREG1$
00066 +A 05b6 b7 65 A STA XREG2$
00066 + ENDC
00066 +A 05b8 b6 b9 A LDA TEMPA$
00066 +A 05ba 3d 61 A TST XREG1$
00067 MACRO INV LDXR #,HIGH0 !-------------------------
00067 + IFEQ NARG-1
00067 + ENDC
00067 + IFEQ NARG-2
00067 + IFC '#','#'
00067 + IFEQ XREG1$!.$FF00 ! XREG in low memory?
00067 + IFEQ HIGH0 ! #0 value?
00067 + ENDC
00067 + IFNE HIGH0 ! not #0 value?
00067 +A 05bc b7 b9 A STA TEMPA$
00067 + IFEQ (HIGH0)!.$FF
00067 +A 05be 3f 62 A CLR XREG1$+1
00067 +A 05c0 3f 66 A CLR XREG2$+1
00067 + ENDC
00067 + IFNE (HIGH0)!.$FF
00067 + ENDC
00067 + IFEQ (HIGH0)!>8
00067 + ENDC
00067 + IFNE (HIGH0)!>8
00067 +A 05c2 a6 1e A LDA #(HIGH0)!>8
00067 +A 05c4 b7 61 A STA XREG1$
00067 +A 05c6 b7 65 A STA XREG2$
00067 + ENDC
00067 +A 05c8 b6 b9 A LDA TEMPA$
00067 +A 05ca 3d 61 A TST XREG1$
00068
00069 MACRO INV STXR LOW !-------------------------
00069 +A 05cc b7 b9 A STA TEMPA$
00069 +A 05ce b6 62 A LDA XREG1$+1
00069 +A 05d0 b7 51 A STA (LOW)+1
00069 +A 05d2 b6 61 A LDA XREG1$
00069 +A 05d4 b7 50 A STA (LOW)
00069 + IFEQ XREG1$!.$FF00
M6805 Portable Cross Assembler 0.05 test1.s Page 21
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00069 +A 05d6 b6 b9 A LDA TEMPA$
00069 +A 05d8 3d 61 A TST XREG1$
00069 + ENDC
00069 + IFNE XREG1$!.$FF00
00069 + ENDC
00070 MACRO INV STXR HIGH !-------------------------
00070 +A 05da b7 b9 A STA TEMPA$
00070 +A 05dc b6 62 A LDA XREG1$+1
00070 +A 05de c7 1eff A STA (HIGH)+1
00070 +A 05e1 b6 61 A LDA XREG1$
00070 +A 05e3 c7 1efe A STA (HIGH)
00070 + IFEQ XREG1$!.$FF00
00070 +A 05e6 b6 b9 A LDA TEMPA$
00070 +A 05e8 3d 61 A TST XREG1$
00070 + ENDC
00070 + IFNE XREG1$!.$FF00
00070 + ENDC
00071
00072 MACRO INV INCXR !-------------------------
00072 + IFEQ NARG
00072 + IFEQ XREG1$!.$FF00
00072 +A 05ea 3c 62 A INC XREG1$+1
00072 +A 05ec 3c 66 A INC XREG2$+1
00072 +A 05ee 26 04 05f4 BNE .00043
00072 +A 05f0 3c 61 A INC XREG1$
00072 +A 05f2 3c 65 A INC XREG2$
00072 +A 05f4 05f4 A .00043 EQU *
00073 MACRO INV INCXR LOW !-------------------------
00073 + IFEQ NARG
00073 + ENDC
00073 + IFEQ NARG-1
00073 +A 05f4 b7 b9 A STA TEMPA$
00073 +A 05f6 b6 62 A LDA XREG1$+1
00073 +A 05f8 bb 51 A ADD (LOW)+1
00073 +A 05fa b7 62 A STA XREG1$+1
00073 +A 05fc b7 66 A STA XREG2$+1
00073 +A 05fe b6 61 A LDA XREG1$
00073 +A 0600 b9 50 A ADC LOW
00073 +A 0602 b7 61 A STA XREG1$
00073 +A 0604 b7 65 A STA XREG2$
00073 +A 0606 ba 62 A ORA XREG1$+1
00073 +A 0608 b7 bd A STA TESTA$
00073 +A 060a b6 b9 A LDA TEMPA$
00073 +A 060c 3d bd A TST TESTA$
00074 MACRO INV INCXR HIGH !-------------------------
00074 + IFEQ NARG
00074 + ENDC
00074 + IFEQ NARG-1
00074 +A 060e b7 b9 A STA TEMPA$
00074 +A 0610 b6 62 A LDA XREG1$+1
00074 +A 0612 cb 1eff A ADD (HIGH)+1
00074 +A 0615 b7 62 A STA XREG1$+1
M6805 Portable Cross Assembler 0.05 test1.s Page 22
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00074 +A 0617 b7 66 A STA XREG2$+1
00074 +A 0619 b6 61 A LDA XREG1$
00074 +A 061b c9 1efe A ADC HIGH
00074 +A 061e b7 61 A STA XREG1$
00074 +A 0620 b7 65 A STA XREG2$
00074 +A 0622 ba 62 A ORA XREG1$+1
00074 +A 0624 b7 bd A STA TESTA$
00074 +A 0626 b6 b9 A LDA TEMPA$
00074 +A 0628 3d bd A TST TESTA$
00075 MACRO INV INCXR #,LOW !-------------------------
00075 + IFEQ NARG
00075 + ENDC
00075 + IFEQ NARG-1
00075 + ENDC
00075 + IFEQ NARG-2
00075 + IFC '#','#'
00075 +A 062a b7 b9 A STA TEMPA$
00075 +A 062c b6 62 A LDA XREG1$+1
00075 +A 062e ab 50 A ADD #(LOW)!.$FF
00075 +A 0630 b7 62 A STA XREG1$+1
00075 +A 0632 b7 66 A STA XREG2$+1
00075 +A 0634 b6 61 A LDA XREG1$
00075 +A 0636 a9 00 A ADC #(LOW)!>8
00075 +A 0638 b7 61 A STA XREG1$
00075 +A 063a b7 65 A STA XREG2$
00075 +A 063c ba 62 A ORA XREG1$+1
00075 +A 063e b7 bd A STA TESTA$
00075 +A 0640 b6 b9 A LDA TEMPA$
00075 +A 0642 3d bd A TST TESTA$
00076 MACRO INV INCXR #,HIGH !-------------------------
00076 + IFEQ NARG
00076 + ENDC
00076 + IFEQ NARG-1
00076 + ENDC
00076 + IFEQ NARG-2
00076 + IFC '#','#'
00076 +A 0644 b7 b9 A STA TEMPA$
00076 +A 0646 b6 62 A LDA XREG1$+1
00076 +A 0648 ab fe A ADD #(HIGH)!.$FF
00076 +A 064a b7 62 A STA XREG1$+1
00076 +A 064c b7 66 A STA XREG2$+1
00076 +A 064e b6 61 A LDA XREG1$
00076 +A 0650 a9 1e A ADC #(HIGH)!>8
00076 +A 0652 b7 61 A STA XREG1$
00076 +A 0654 b7 65 A STA XREG2$
00076 +A 0656 ba 62 A ORA XREG1$+1
00076 +A 0658 b7 bd A STA TESTA$
00076 +A 065a b6 b9 A LDA TEMPA$
00076 +A 065c 3d bd A TST TESTA$
00077
00078 MACRO INV DECXR !-------------------------
00078 + IFEQ NARG
M6805 Portable Cross Assembler 0.05 test1.s Page 23
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00078 +A 065e b7 b9 A STA TEMPA$
00078 +A 0660 b6 62 A LDA XREG1$+1
00078 +A 0662 a0 01 A SUB #1
00078 +A 0664 b7 62 A STA XREG1$+1
00078 +A 0666 b7 66 A STA XREG2$+1
00078 +A 0668 b6 61 A LDA XREG1$
00078 +A 066a a2 00 A SBC #0
00078 +A 066c b7 61 A STA XREG1$
00078 +A 066e b7 65 A STA XREG2$
00078 +A 0670 ba 62 A ORA XREG1$+1
00078 +A 0672 b7 bd A STA TESTA$
00078 +A 0674 b6 b9 A LDA TEMPA$
00078 +A 0676 3d bd A TST TESTA$
00079 MACRO INV DECXR LOW !-------------------------
00079 + IFEQ NARG
00079 + ENDC
00079 + IFEQ NARG-1
00079 +A 0678 b7 b9 A STA TEMPA$
00079 +A 067a b6 62 A LDA XREG1$+1
00079 +A 067c b0 51 A SUB (LOW)+1
00079 +A 067e b7 62 A STA XREG1$+1
00079 +A 0680 b7 66 A STA XREG2$+1
00079 +A 0682 b6 61 A LDA XREG1$
00079 +A 0684 b2 50 A SBC LOW
00079 +A 0686 b7 61 A STA XREG1$
00079 +A 0688 b7 65 A STA XREG2$
00079 +A 068a ba 62 A ORA XREG1$+1
00079 +A 068c b7 bd A STA TESTA$
00079 +A 068e b6 b9 A LDA TEMPA$
00079 +A 0690 3d bd A TST TESTA$
00080 MACRO INV DECXR HIGH !-------------------------
00080 + IFEQ NARG
00080 + ENDC
00080 + IFEQ NARG-1
00080 +A 0692 b7 b9 A STA TEMPA$
00080 +A 0694 b6 62 A LDA XREG1$+1
00080 +A 0696 c0 1eff A SUB (HIGH)+1
00080 +A 0699 b7 62 A STA XREG1$+1
00080 +A 069b b7 66 A STA XREG2$+1
00080 +A 069d b6 61 A LDA XREG1$
00080 +A 069f c2 1efe A SBC HIGH
00080 +A 06a2 b7 61 A STA XREG1$
00080 +A 06a4 b7 65 A STA XREG2$
00080 +A 06a6 ba 62 A ORA XREG1$+1
00080 +A 06a8 b7 bd A STA TESTA$
00080 +A 06aa b6 b9 A LDA TEMPA$
00080 +A 06ac 3d bd A TST TESTA$
00081 MACRO INV DECXR #,LOW !-------------------------
00081 + IFEQ NARG
00081 + ENDC
00081 + IFEQ NARG-1
00081 + ENDC
M6805 Portable Cross Assembler 0.05 test1.s Page 24
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00081 + IFEQ NARG-2
00081 + IFC '#','#'
00081 +A 06ae b7 b9 A STA TEMPA$
00081 +A 06b0 b6 62 A LDA XREG1$+1
00081 +A 06b2 a0 50 A SUB #(LOW)!.$FF
00081 +A 06b4 b7 62 A STA XREG1$+1
00081 +A 06b6 b7 66 A STA XREG2$+1
00081 +A 06b8 b6 61 A LDA XREG1$
00081 +A 06ba a2 00 A SBC #(LOW)!>8
00081 +A 06bc b7 61 A STA XREG1$
00081 +A 06be b7 65 A STA XREG2$
00081 +A 06c0 ba 62 A ORA XREG1$+1
00081 +A 06c2 b7 bd A STA TESTA$
00081 +A 06c4 b6 b9 A LDA TEMPA$
00081 +A 06c6 3d bd A TST TESTA$
00082 MACRO INV DECXR #,HIGH !-------------------------
00082 + IFEQ NARG
00082 + ENDC
00082 + IFEQ NARG-1
00082 + ENDC
00082 + IFEQ NARG-2
00082 + IFC '#','#'
00082 +A 06c8 b7 b9 A STA TEMPA$
00082 +A 06ca b6 62 A LDA XREG1$+1
00082 +A 06cc a0 fe A SUB #(HIGH)!.$FF
00082 +A 06ce b7 62 A STA XREG1$+1
00082 +A 06d0 b7 66 A STA XREG2$+1
00082 +A 06d2 b6 61 A LDA XREG1$
00082 +A 06d4 a2 1e A SBC #(HIGH)!>8
00082 +A 06d6 b7 61 A STA XREG1$
00082 +A 06d8 b7 65 A STA XREG2$
00082 +A 06da ba 62 A ORA XREG1$+1
00082 +A 06dc b7 bd A STA TESTA$
00082 +A 06de b6 b9 A LDA TEMPA$
00082 +A 06e0 3d bd A TST TESTA$
00083
00084 MACRO INV CPXR ZERO !-------------------------
00084 + IFEQ NARG-1
00084 +A 06e2 b7 b9 A STA TEMPA$
00084 +A 06e4 10 bd A BSET 0,TESTA$ Preset for .NE. condition!
00084 +A 06e6 b6 62 A LDA XREG1$+1
00084 +A 06e8 b1 01 A CMP (ZERO)+1
00084 +A 06ea 26 08 06f4 BNE .00053 Branch if LS half is .NE.
00084 +A 06ec b6 61 A LDA XREG1$
00084 +A 06ee b1 00 A CMP (ZERO)
00084 +A 06f0 26 02 06f4 BNE .00053 Branch if MS half is .NE.
00084 +A 06f2 3f bd A CLR TESTA$ Set for .EQ. condition!
00084 +A 06f4 b6 b9 A .00053 LDA TEMPA$
00084 +A 06f6 3d bd A TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
00085 MACRO INV CPXR LOW !-------------------------
00085 + IFEQ NARG-1
00085 +A 06f8 b7 b9 A STA TEMPA$
M6805 Portable Cross Assembler 0.05 test1.s Page 25
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00085 +A 06fa 10 bd A BSET 0,TESTA$ Preset for .NE. condition!
00085 +A 06fc b6 62 A LDA XREG1$+1
00085 +A 06fe b1 51 A CMP (LOW)+1
00085 +A 0700 26 08 070a BNE .00054 Branch if LS half is .NE.
00085 +A 0702 b6 61 A LDA XREG1$
00085 +A 0704 b1 50 A CMP (LOW)
00085 +A 0706 26 02 070a BNE .00054 Branch if MS half is .NE.
00085 +A 0708 3f bd A CLR TESTA$ Set for .EQ. condition!
00085 +A 070a b6 b9 A .00054 LDA TEMPA$
00085 +A 070c 3d bd A TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
00086 MACRO INV CPXR HIGH !-------------------------
00086 + IFEQ NARG-1
00086 +A 070e b7 b9 A STA TEMPA$
00086 +A 0710 10 bd A BSET 0,TESTA$ Preset for .NE. condition!
00086 +A 0712 b6 62 A LDA XREG1$+1
00086 +A 0714 c1 1eff A CMP (HIGH)+1
00086 +A 0717 26 09 0722 BNE .00055 Branch if LS half is .NE.
00086 +A 0719 b6 61 A LDA XREG1$
00086 +A 071b c1 1efe A CMP (HIGH)
00086 +A 071e 26 02 0722 BNE .00055 Branch if MS half is .NE.
00086 +A 0720 3f bd A CLR TESTA$ Set for .EQ. condition!
00086 +A 0722 b6 b9 A .00055 LDA TEMPA$
00086 +A 0724 3d bd A TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
00087 MACRO INV CPXR #,0 !-------------------------
00087 + IFEQ NARG-1
00087 + ENDC
00087 + IFEQ NARG-2
00087 + IFC '#','#'
00087 + IFEQ 0
00087 + IFEQ XREG1$!.$FF00
00087 +A 0726 3d 62 A TST XREG1$+1
00087 +A 0728 26 02 072c BNE .00056 Branch if LS half is .NE.
00087 +A 072a 3d 61 A TST XREG1$
00087 +A 072c 072c A .00056 EQU *
00088 MACRO INV CPXR #,LOW !-------------------------
00088 + IFEQ NARG-1
00088 + ENDC
00088 + IFEQ NARG-2
00088 + IFC '#','#'
00088 + IFEQ LOW
00088 + ENDC
00088 +A 072c b7 b9 A STA TEMPA$
00088 +A 072e 10 bd A BSET 0,TESTA$ Preset for .NE. condition!
00088 +A 0730 b6 62 A LDA XREG1$+1
00088 + IFNE (LOW)!.$FF
00088 +A 0732 a1 50 A CMP #(LOW)!.$FF
00088 + ENDC
00088 +A 0734 26 06 073c BNE .00057 Branch if LS half is .NE.
00088 +A 0736 b6 61 A LDA XREG1$
00088 + IFNE (LOW)!>8
00088 + ENDC
00088 +A 0738 26 02 073c BNE .00057 Branch if MS half is .NE.
M6805 Portable Cross Assembler 0.05 test1.s Page 26
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00088 +A 073a 3f bd A CLR TESTA$ Set for .EQ. condition!
00088 +A 073c b6 b9 A .00057 LDA TEMPA$
00088 +A 073e 3d bd A TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
00089 MACRO INV CPXR #,HIGH !-------------------------
00089 + IFEQ NARG-1
00089 + ENDC
00089 + IFEQ NARG-2
00089 + IFC '#','#'
00089 + IFEQ HIGH
00089 + ENDC
00089 +A 0740 b7 b9 A STA TEMPA$
00089 +A 0742 10 bd A BSET 0,TESTA$ Preset for .NE. condition!
00089 +A 0744 b6 62 A LDA XREG1$+1
00089 + IFNE (HIGH)!.$FF
00089 +A 0746 a1 fe A CMP #(HIGH)!.$FF
00089 + ENDC
00089 +A 0748 26 08 0752 BNE .00058 Branch if LS half is .NE.
00089 +A 074a b6 61 A LDA XREG1$
00089 + IFNE (HIGH)!>8
00089 +A 074c a1 1e A CMP #(HIGH)!>8
00089 + ENDC
00089 +A 074e 26 02 0752 BNE .00058 Branch if MS half is .NE.
00089 +A 0750 3f bd A CLR TESTA$ Set for .EQ. condition!
00089 +A 0752 b6 b9 A .00058 LDA TEMPA$
00089 +A 0754 3d bd A TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
00090 MACRO INV CPXR #,HIGH0 !-------------------------
00090 + IFEQ NARG-1
00090 + ENDC
00090 + IFEQ NARG-2
00090 + IFC '#','#'
00090 + IFEQ HIGH0
00090 + ENDC
00090 +A 0756 b7 b9 A STA TEMPA$
00090 +A 0758 10 bd A BSET 0,TESTA$ Preset for .NE. condition!
00090 +A 075a b6 62 A LDA XREG1$+1
00090 + IFNE (HIGH0)!.$FF
00090 + ENDC
00090 +A 075c 26 08 0766 BNE .00059 Branch if LS half is .NE.
00090 +A 075e b6 61 A LDA XREG1$
00090 + IFNE (HIGH0)!>8
00090 +A 0760 a1 1e A CMP #(HIGH0)!>8
00090 + ENDC
00090 +A 0762 26 02 0766 BNE .00059 Branch if MS half is .NE.
00090 +A 0764 3f bd A CLR TESTA$ Set for .EQ. condition!
00090 +A 0766 b6 b9 A .00059 LDA TEMPA$
00090 +A 0768 3d bd A TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
00091
00092 * @@@@@@@@ YREG tests start here
00093 MACRO INV LDAXY ,YREG !-------------------------
00093 + IFNC 'YREG','XREG'
00093 + IFNC 'YREG','YREG'
00093 + ENDC
M6805 Portable Cross Assembler 0.05 test1.s Page 27
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00093 + ENDC
00093 + IFC '',''
00093 +A 076a bd 68 A JSR LDAYREG Default offset= 0
00094 MACRO INV LDAXY 0,YREG !-------------------------
00094 + IFNC 'YREG','XREG'
00094 + IFNC 'YREG','YREG'
00094 + ENDC
00094 + ENDC
00094 + IFC '0',''
00094 + ENDC
00094 + IFNC '0',''
00094 + IFEQ 0
00094 +A 076c bd 68 A JSR LDAYREG Offset= 0
00095 MACRO INV LDAXY 5,YREG !-------------------------
00095 + IFNC 'YREG','XREG'
00095 + IFNC 'YREG','YREG'
00095 + ENDC
00095 + ENDC
00095 + IFC '5',''
00095 + ENDC
00095 + IFNC '5',''
00095 + IFEQ 5
00095 + ENDC
00095 + IFNE 5
00095 +A 076e b6 6a A LDA YREG1$+1 Set nREG= offset + nREG
00095 +A 0770 ab 05 A ADD #(5)!.$FF
00095 +A 0772 b7 6a A STA YREG1$+1
00095 +A 0774 b6 69 A LDA YREG1$
00095 +A 0776 a9 00 A ADC #(5)!>8
00095 +A 0778 b7 69 A STA YREG1$
00095 +A 077a bd 68 A JSR LDAYREG Offset= 0
00095 +A 077c b7 b9 A STA TEMPA$
00095 +A 077e b6 6d A LDA YREG2$ Restore nREG
00095 +A 0780 b7 69 A STA YREG1$
00095 +A 0782 b6 6e A LDA YREG2$+1
00095 +A 0784 b7 6a A STA YREG1$+1
00095 +A 0786 b6 b9 A LDA TEMPA$
00096 MACRO INV LDAXY LOW,YREG !------------------------
00096 + IFNC 'YREG','XREG'
00096 + IFNC 'YREG','YREG'
00096 + ENDC
00096 + ENDC
00096 + IFC 'LOW',''
00096 + ENDC
00096 + IFNC 'LOW',''
00096 + IFEQ LOW
00096 + ENDC
00096 + IFNE LOW
00096 +A 0788 b6 6a A LDA YREG1$+1 Set nREG= offset + nREG
00096 +A 078a ab 50 A ADD #(LOW)!.$FF
00096 +A 078c b7 6a A STA YREG1$+1
00096 +A 078e b6 69 A LDA YREG1$
M6805 Portable Cross Assembler 0.05 test1.s Page 28
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00096 +A 0790 a9 00 A ADC #(LOW)!>8
00096 +A 0792 b7 69 A STA YREG1$
00096 +A 0794 bd 68 A JSR LDAYREG Offset= 0
00096 +A 0796 b7 b9 A STA TEMPA$
00096 +A 0798 b6 6d A LDA YREG2$ Restore nREG
00096 +A 079a b7 69 A STA YREG1$
00096 +A 079c b6 6e A LDA YREG2$+1
00096 +A 079e b7 6a A STA YREG1$+1
00096 +A 07a0 b6 b9 A LDA TEMPA$
00097 MACRO INV LDAXY HIGH,YREG !-----------------------
00097 + IFNC 'YREG','XREG'
00097 + IFNC 'YREG','YREG'
00097 + ENDC
00097 + ENDC
00097 + IFC 'HIGH',''
00097 + ENDC
00097 + IFNC 'HIGH',''
00097 + IFEQ HIGH
00097 + ENDC
00097 + IFNE HIGH
00097 +A 07a2 b6 6a A LDA YREG1$+1 Set nREG= offset + nREG
00097 +A 07a4 ab fe A ADD #(HIGH)!.$FF
00097 +A 07a6 b7 6a A STA YREG1$+1
00097 +A 07a8 b6 69 A LDA YREG1$
00097 +A 07aa a9 1e A ADC #(HIGH)!>8
00097 +A 07ac b7 69 A STA YREG1$
00097 +A 07ae bd 68 A JSR LDAYREG Offset= 0
00097 +A 07b0 b7 b9 A STA TEMPA$
00097 +A 07b2 b6 6d A LDA YREG2$ Restore nREG
00097 +A 07b4 b7 69 A STA YREG1$
00097 +A 07b6 b6 6e A LDA YREG2$+1
00097 +A 07b8 b7 6a A STA YREG1$+1
00097 +A 07ba b6 b9 A LDA TEMPA$
00098
00099 MACRO INV STAXY ,YREG !-------------------------
00099 + IFNC 'YREG','XREG'
00099 + IFNC 'YREG','YREG'
00099 + ENDC
00099 + ENDC
00099 + IFC '',''
00099 +A 07bc bd 6c A JSR STAYREG Default offset= 0
00100 MACRO INV STAXY 0,YREG !-------------------------
00100 + IFNC 'YREG','XREG'
00100 + IFNC 'YREG','YREG'
00100 + ENDC
00100 + ENDC
00100 + IFC '0',''
00100 + ENDC
00100 + IFNC '0',''
00100 + IFEQ 0
00100 +A 07be bd 6c A JSR STAYREG Offset= 0
00101 MACRO INV STAXY 5,YREG !-------------------------
M6805 Portable Cross Assembler 0.05 test1.s Page 29
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00101 + IFNC 'YREG','XREG'
00101 + IFNC 'YREG','YREG'
00101 + ENDC
00101 + ENDC
00101 + IFC '5',''
00101 + ENDC
00101 + IFNC '5',''
00101 + IFEQ 5
00101 + ENDC
00101 + IFNE 5
00101 +A 07c0 b7 b9 A STA TEMPA$
00101 +A 07c2 b6 6e A LDA YREG2$+1 Set nREG= offset + nREG
00101 +A 07c4 ab 05 A ADD #(5)!.$FF
00101 +A 07c6 b7 6e A STA YREG2$+1
00101 +A 07c8 b6 6d A LDA YREG2$
00101 +A 07ca a9 00 A ADC #(5)!>8
00101 +A 07cc b7 6d A STA YREG2$
00101 +A 07ce b6 b9 A LDA TEMPA$
00101 +A 07d0 bd 6c A JSR STAYREG Offset= 0
00101 +A 07d2 b6 69 A LDA YREG1$ Restore nREG
00101 +A 07d4 b7 6d A STA YREG2$
00101 +A 07d6 b6 6a A LDA YREG1$+1
00101 +A 07d8 b7 6e A STA YREG2$+1
00101 +A 07da b6 b9 A LDA TEMPA$
00102 MACRO INV STAXY LOW,YREG !------------------------
00102 + IFNC 'YREG','XREG'
00102 + IFNC 'YREG','YREG'
00102 + ENDC
00102 + ENDC
00102 + IFC 'LOW',''
00102 + ENDC
00102 + IFNC 'LOW',''
00102 + IFEQ LOW
00102 + ENDC
00102 + IFNE LOW
00102 +A 07dc b7 b9 A STA TEMPA$
00102 +A 07de b6 6e A LDA YREG2$+1 Set nREG= offset + nREG
00102 +A 07e0 ab 50 A ADD #(LOW)!.$FF
00102 +A 07e2 b7 6e A STA YREG2$+1
00102 +A 07e4 b6 6d A LDA YREG2$
00102 +A 07e6 a9 00 A ADC #(LOW)!>8
00102 +A 07e8 b7 6d A STA YREG2$
00102 +A 07ea b6 b9 A LDA TEMPA$
00102 +A 07ec bd 6c A JSR STAYREG Offset= 0
00102 +A 07ee b6 69 A LDA YREG1$ Restore nREG
00102 +A 07f0 b7 6d A STA YREG2$
00102 +A 07f2 b6 6a A LDA YREG1$+1
00102 +A 07f4 b7 6e A STA YREG2$+1
00102 +A 07f6 b6 b9 A LDA TEMPA$
00103 MACRO INV STAXY HIGH,YREG !-----------------------
00103 + IFNC 'YREG','XREG'
00103 + IFNC 'YREG','YREG'
M6805 Portable Cross Assembler 0.05 test1.s Page 30
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00103 + ENDC
00103 + ENDC
00103 + IFC 'HIGH',''
00103 + ENDC
00103 + IFNC 'HIGH',''
00103 + IFEQ HIGH
00103 + ENDC
00103 + IFNE HIGH
00103 +A 07f8 b7 b9 A STA TEMPA$
00103 +A 07fa b6 6e A LDA YREG2$+1 Set nREG= offset + nREG
00103 +A 07fc ab fe A ADD #(HIGH)!.$FF
00103 +A 07fe b7 6e A STA YREG2$+1
00103 +A 0800 b6 6d A LDA YREG2$
00103 +A 0802 a9 1e A ADC #(HIGH)!>8
00103 +A 0804 b7 6d A STA YREG2$
00103 +A 0806 b6 b9 A LDA TEMPA$
00103 +A 0808 bd 6c A JSR STAYREG Offset= 0
00103 +A 080a b6 69 A LDA YREG1$ Restore nREG
00103 +A 080c b7 6d A STA YREG2$
00103 +A 080e b6 6a A LDA YREG1$+1
00103 +A 0810 b7 6e A STA YREG2$+1
00103 +A 0812 b6 b9 A LDA TEMPA$
00104
00105 MACRO INV LDYR ZERO !-------------------------
00105 + IFEQ NARG-1
00105 +A 0814 b7 b9 A STA TEMPA$
00105 +A 0816 b6 00 A LDA (ZERO)
00105 +A 0818 b7 69 A STA YREG1$
00105 +A 081a b7 6d A STA YREG2$
00105 +A 081c b6 01 A LDA (ZERO)+1
00105 +A 081e b7 6a A STA YREG1$+1
00105 +A 0820 b7 6e A STA YREG2$+1
00105 + IFEQ YREG1$!.$FF00
00105 +A 0822 b6 b9 A LDA TEMPA$
00105 +A 0824 3d 69 A TST YREG1$
00105 + ENDC
00105 + IFNE YREG1$!.$FF00
00105 + ENDC
00106 MACRO INV LDYR LOW !-------------------------
00106 + IFEQ NARG-1
00106 +A 0826 b7 b9 A STA TEMPA$
00106 +A 0828 b6 50 A LDA (LOW)
00106 +A 082a b7 69 A STA YREG1$
00106 +A 082c b7 6d A STA YREG2$
00106 +A 082e b6 51 A LDA (LOW)+1
00106 +A 0830 b7 6a A STA YREG1$+1
00106 +A 0832 b7 6e A STA YREG2$+1
00106 + IFEQ YREG1$!.$FF00
00106 +A 0834 b6 b9 A LDA TEMPA$
00106 +A 0836 3d 69 A TST YREG1$
00106 + ENDC
00106 + IFNE YREG1$!.$FF00
M6805 Portable Cross Assembler 0.05 test1.s Page 31
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00106 + ENDC
00107 MACRO INV LDYR HIGH !-------------------------
00107 + IFEQ NARG-1
00107 +A 0838 b7 b9 A STA TEMPA$
00107 +A 083a c6 1efe A LDA (HIGH)
00107 +A 083d b7 69 A STA YREG1$
00107 +A 083f b7 6d A STA YREG2$
00107 +A 0841 c6 1eff A LDA (HIGH)+1
00107 +A 0844 b7 6a A STA YREG1$+1
00107 +A 0846 b7 6e A STA YREG2$+1
00107 + IFEQ YREG1$!.$FF00
00107 +A 0848 b6 b9 A LDA TEMPA$
00107 +A 084a 3d 69 A TST YREG1$
00107 + ENDC
00107 + IFNE YREG1$!.$FF00
00107 + ENDC
00108 MACRO INV LDYR #,0 !-------------------------
00108 + IFEQ NARG-1
00108 + ENDC
00108 + IFEQ NARG-2
00108 + IFC '#','#'
00108 + IFEQ YREG1$!.$FF00 ! YREG in low memory?
00108 + IFEQ 0 ! #0 value?
00108 +A 084c 3f 6a A CLR YREG1$+1
00108 +A 084e 3f 6e A CLR YREG2$+1
00108 +A 0850 3f 69 A CLR YREG1$
00108 +A 0852 3f 6d A CLR YREG2$
00109 MACRO INV LDYR #,LOW !-------------------------
00109 + IFEQ NARG-1
00109 + ENDC
00109 + IFEQ NARG-2
00109 + IFC '#','#'
00109 + IFEQ YREG1$!.$FF00 ! YREG in low memory?
00109 + IFEQ LOW ! #0 value?
00109 + ENDC
00109 + IFNE LOW ! not #0 value?
00109 +A 0854 b7 b9 A STA TEMPA$
00109 + IFEQ (LOW)!.$FF
00109 + ENDC
00109 + IFNE (LOW)!.$FF
00109 +A 0856 a6 50 A LDA #(LOW)!.$FF
00109 +A 0858 b7 6a A STA YREG1$+1
00109 +A 085a b7 6e A STA YREG2$+1
00109 + ENDC
00109 + IFEQ (LOW)!>8
00109 +A 085c 3f 69 A CLR YREG1$
00109 +A 085e 3f 6d A CLR YREG2$
00109 + ENDC
00109 + IFNE (LOW)!>8
00109 + ENDC
00109 +A 0860 b6 b9 A LDA TEMPA$
00109 +A 0862 3d 69 A TST YREG1$
M6805 Portable Cross Assembler 0.05 test1.s Page 32
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00110 MACRO INV LDYR #,HIGH !-------------------------
00110 + IFEQ NARG-1
00110 + ENDC
00110 + IFEQ NARG-2
00110 + IFC '#','#'
00110 + IFEQ YREG1$!.$FF00 ! YREG in low memory?
00110 + IFEQ HIGH ! #0 value?
00110 + ENDC
00110 + IFNE HIGH ! not #0 value?
00110 +A 0864 b7 b9 A STA TEMPA$
00110 + IFEQ (HIGH)!.$FF
00110 + ENDC
00110 + IFNE (HIGH)!.$FF
00110 +A 0866 a6 fe A LDA #(HIGH)!.$FF
00110 +A 0868 b7 6a A STA YREG1$+1
00110 +A 086a b7 6e A STA YREG2$+1
00110 + ENDC
00110 + IFEQ (HIGH)!>8
00110 + ENDC
00110 + IFNE (HIGH)!>8
00110 +A 086c a6 1e A LDA #(HIGH)!>8
00110 +A 086e b7 69 A STA YREG1$
00110 +A 0870 b7 6d A STA YREG2$
00110 + ENDC
00110 +A 0872 b6 b9 A LDA TEMPA$
00110 +A 0874 3d 69 A TST YREG1$
00111 MACRO INV LDYR #,HIGH0 !-------------------------
00111 + IFEQ NARG-1
00111 + ENDC
00111 + IFEQ NARG-2
00111 + IFC '#','#'
00111 + IFEQ YREG1$!.$FF00 ! YREG in low memory?
00111 + IFEQ HIGH0 ! #0 value?
00111 + ENDC
00111 + IFNE HIGH0 ! not #0 value?
00111 +A 0876 b7 b9 A STA TEMPA$
00111 + IFEQ (HIGH0)!.$FF
00111 +A 0878 3f 6a A CLR YREG1$+1
00111 +A 087a 3f 6e A CLR YREG2$+1
00111 + ENDC
00111 + IFNE (HIGH0)!.$FF
00111 + ENDC
00111 + IFEQ (HIGH0)!>8
00111 + ENDC
00111 + IFNE (HIGH0)!>8
00111 +A 087c a6 1e A LDA #(HIGH0)!>8
00111 +A 087e b7 69 A STA YREG1$
00111 +A 0880 b7 6d A STA YREG2$
00111 + ENDC
00111 +A 0882 b6 b9 A LDA TEMPA$
00111 +A 0884 3d 69 A TST YREG1$
00112
M6805 Portable Cross Assembler 0.05 test1.s Page 33
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00113 MACRO INV STYR LOW !-------------------------
00113 +A 0886 b7 b9 A STA TEMPA$
00113 +A 0888 b6 69 A LDA YREG1$
00113 +A 088a b7 50 A STA (LOW)
00113 +A 088c b6 6a A LDA YREG1$+1
00113 +A 088e b7 51 A STA (LOW)+1
00113 + IFEQ YREG1$!.$FF00
00113 +A 0890 b6 b9 A LDA TEMPA$
00113 +A 0892 3d 69 A TST YREG1$
00113 + ENDC
00113 + IFNE YREG1$!.$FF00
00113 + ENDC
00114 MACRO INV STYR HIGH !-------------------------
00114 +A 0894 b7 b9 A STA TEMPA$
00114 +A 0896 b6 69 A LDA YREG1$
00114 +A 0898 c7 1efe A STA (HIGH)
00114 +A 089b b6 6a A LDA YREG1$+1
00114 +A 089d c7 1eff A STA (HIGH)+1
00114 + IFEQ YREG1$!.$FF00
00114 +A 08a0 b6 b9 A LDA TEMPA$
00114 +A 08a2 3d 69 A TST YREG1$
00114 + ENDC
00114 + IFNE YREG1$!.$FF00
00114 + ENDC
00115
00116 MACRO INV INCYR !-------------------------
00116 + IFEQ NARG
00116 + IFEQ YREG1$!.$FF00
00116 +A 08a4 3c 6a A INC YREG1$+1
00116 +A 08a6 3c 6e A INC YREG2$+1
00116 +A 08a8 26 04 08ae BNE .00079
00116 +A 08aa 3c 69 A INC YREG1$
00116 +A 08ac 3c 6d A INC YREG2$
00116 +A 08ae 08ae A .00079 EQU *
00117 MACRO INV INCYR LOW !-------------------------
00117 + IFEQ NARG
00117 + ENDC
00117 + IFEQ NARG-1
00117 +A 08ae b7 b9 A STA TEMPA$
00117 +A 08b0 b6 6a A LDA YREG1$+1
00117 +A 08b2 bb 51 A ADD (LOW)+1
00117 +A 08b4 b7 6a A STA YREG1$+1
00117 +A 08b6 b7 6e A STA YREG2$+1
00117 +A 08b8 b6 69 A LDA YREG1$
00117 +A 08ba b9 50 A ADC LOW
00117 +A 08bc b7 69 A STA YREG1$
00117 +A 08be b7 6d A STA YREG2$
00117 +A 08c0 ba 6a A ORA YREG1$+1
00117 +A 08c2 b7 bd A STA TESTA$
00117 +A 08c4 b6 b9 A LDA TEMPA$
00117 +A 08c6 3d bd A TST TESTA$
00118 MACRO INV INCYR HIGH !-------------------------
M6805 Portable Cross Assembler 0.05 test1.s Page 34
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00118 + IFEQ NARG
00118 + ENDC
00118 + IFEQ NARG-1
00118 +A 08c8 b7 b9 A STA TEMPA$
00118 +A 08ca b6 6a A LDA YREG1$+1
00118 +A 08cc cb 1eff A ADD (HIGH)+1
00118 +A 08cf b7 6a A STA YREG1$+1
00118 +A 08d1 b7 6e A STA YREG2$+1
00118 +A 08d3 b6 69 A LDA YREG1$
00118 +A 08d5 c9 1efe A ADC HIGH
00118 +A 08d8 b7 69 A STA YREG1$
00118 +A 08da b7 6d A STA YREG2$
00118 +A 08dc ba 6a A ORA YREG1$+1
00118 +A 08de b7 bd A STA TESTA$
00118 +A 08e0 b6 b9 A LDA TEMPA$
00118 +A 08e2 3d bd A TST TESTA$
00119 MACRO INV INCYR #,LOW !-------------------------
00119 + IFEQ NARG
00119 + ENDC
00119 + IFEQ NARG-1
00119 + ENDC
00119 + IFEQ NARG-2
00119 + IFC '#','#'
00119 +A 08e4 b7 b9 A STA TEMPA$
00119 +A 08e6 b6 6a A LDA YREG1$+1
00119 +A 08e8 ab 50 A ADD #(LOW)!.$FF
00119 +A 08ea b7 6a A STA YREG1$+1
00119 +A 08ec b7 6e A STA YREG2$+1
00119 +A 08ee b6 69 A LDA YREG1$
00119 +A 08f0 a9 00 A ADC #(LOW)!>8
00119 +A 08f2 b7 69 A STA YREG1$
00119 +A 08f4 b7 6d A STA YREG2$
00119 +A 08f6 ba 62 A ORA XREG1$+1
00119 +A 08f8 b7 bd A STA TESTA$
00119 +A 08fa b6 b9 A LDA TEMPA$
00119 +A 08fc 3d bd A TST TESTA$
00120 MACRO INV INCYR #,HIGH !-------------------------
00120 + IFEQ NARG
00120 + ENDC
00120 + IFEQ NARG-1
00120 + ENDC
00120 + IFEQ NARG-2
00120 + IFC '#','#'
00120 +A 08fe b7 b9 A STA TEMPA$
00120 +A 0900 b6 6a A LDA YREG1$+1
00120 +A 0902 ab fe A ADD #(HIGH)!.$FF
00120 +A 0904 b7 6a A STA YREG1$+1
00120 +A 0906 b7 6e A STA YREG2$+1
00120 +A 0908 b6 69 A LDA YREG1$
00120 +A 090a a9 1e A ADC #(HIGH)!>8
00120 +A 090c b7 69 A STA YREG1$
00120 +A 090e b7 6d A STA YREG2$
M6805 Portable Cross Assembler 0.05 test1.s Page 35
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00120 +A 0910 ba 62 A ORA XREG1$+1
00120 +A 0912 b7 bd A STA TESTA$
00120 +A 0914 b6 b9 A LDA TEMPA$
00120 +A 0916 3d bd A TST TESTA$
00121
00122 MACRO INV DECYR !-------------------------
00122 + IFEQ NARG
00122 +A 0918 b7 b9 A STA TEMPA$
00122 +A 091a b6 6a A LDA YREG1$+1
00122 +A 091c a0 01 A SUB #1
00122 +A 091e b7 6a A STA YREG1$+1
00122 +A 0920 b7 6e A STA YREG2$+1
00122 +A 0922 b6 69 A LDA YREG1$
00122 +A 0924 a2 00 A SBC #0
00122 +A 0926 b7 69 A STA YREG1$
00122 +A 0928 b7 6d A STA YREG2$
00122 +A 092a ba 6a A ORA YREG1$+1
00122 +A 092c b7 bd A STA TESTA$
00122 +A 092e b6 b9 A LDA TEMPA$
00122 +A 0930 3d bd A TST TESTA$
00123 MACRO INV DECYR LOW !-------------------------
00123 + IFEQ NARG
00123 + ENDC
00123 + IFEQ NARG-1
00123 +A 0932 b7 b9 A STA TEMPA$
00123 +A 0934 b6 6a A LDA YREG1$+1
00123 +A 0936 b0 51 A SUB (LOW)+1
00123 +A 0938 b7 6a A STA YREG1$+1
00123 +A 093a b7 6e A STA YREG2$+1
00123 +A 093c b6 69 A LDA YREG1$
00123 +A 093e b2 50 A SBC LOW
00123 +A 0940 b7 69 A STA YREG1$
00123 +A 0942 b7 6d A STA YREG2$
00123 +A 0944 ba 6a A ORA YREG1$+1
00123 +A 0946 b7 bd A STA TESTA$
00123 +A 0948 b6 b9 A LDA TEMPA$
00123 +A 094a 3d bd A TST TESTA$
00124 MACRO INV DECYR HIGH !-------------------------
00124 + IFEQ NARG
00124 + ENDC
00124 + IFEQ NARG-1
00124 +A 094c b7 b9 A STA TEMPA$
00124 +A 094e b6 6a A LDA YREG1$+1
00124 +A 0950 c0 1eff A SUB (HIGH)+1
00124 +A 0953 b7 6a A STA YREG1$+1
00124 +A 0955 b7 6e A STA YREG2$+1
00124 +A 0957 b6 69 A LDA YREG1$
00124 +A 0959 c2 1efe A SBC HIGH
00124 +A 095c b7 69 A STA YREG1$
00124 +A 095e b7 6d A STA YREG2$
00124 +A 0960 ba 6a A ORA YREG1$+1
00124 +A 0962 b7 bd A STA TESTA$
M6805 Portable Cross Assembler 0.05 test1.s Page 36
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00124 +A 0964 b6 b9 A LDA TEMPA$
00124 +A 0966 3d bd A TST TESTA$
00125 MACRO INV DECYR #,LOW !-------------------------
00125 + IFEQ NARG
00125 + ENDC
00125 + IFEQ NARG-1
00125 + ENDC
00125 + IFEQ NARG-2
00125 + IFC '#','#'
00125 +A 0968 b7 b9 A STA TEMPA$
00125 +A 096a b6 6a A LDA YREG1$+1
00125 +A 096c a0 50 A SUB #(LOW)!.$FF
00125 +A 096e b7 6a A STA YREG1$+1
00125 +A 0970 b7 6e A STA YREG2$+1
00125 +A 0972 b6 69 A LDA YREG1$
00125 +A 0974 a2 00 A SBC #(LOW)!>8
00125 +A 0976 b7 69 A STA YREG1$
00125 +A 0978 b7 6d A STA YREG2$
00125 +A 097a ba 6a A ORA YREG1$+1
00125 +A 097c b7 bd A STA TESTA$
00125 +A 097e b6 b9 A LDA TEMPA$
00125 +A 0980 3d bd A TST TESTA$
00126 MACRO INV DECYR #,HIGH !-------------------------
00126 + IFEQ NARG
00126 + ENDC
00126 + IFEQ NARG-1
00126 + ENDC
00126 + IFEQ NARG-2
00126 + IFC '#','#'
00126 +A 0982 b7 b9 A STA TEMPA$
00126 +A 0984 b6 6a A LDA YREG1$+1
00126 +A 0986 a0 fe A SUB #(HIGH)!.$FF
00126 +A 0988 b7 6a A STA YREG1$+1
00126 +A 098a b7 6e A STA YREG2$+1
00126 +A 098c b6 69 A LDA YREG1$
00126 +A 098e a2 1e A SBC #(HIGH)!>8
00126 +A 0990 b7 69 A STA YREG1$
00126 +A 0992 b7 6d A STA YREG2$
00126 +A 0994 ba 6a A ORA YREG1$+1
00126 +A 0996 b7 bd A STA TESTA$
00126 +A 0998 b6 b9 A LDA TEMPA$
00126 +A 099a 3d bd A TST TESTA$
00127
00128 MACRO INV CPYR ZERO !-------------------------
00128 + IFEQ NARG-1
00128 +A 099c b7 b9 A STA TEMPA$
00128 +A 099e 10 bd A BSET 0,TESTA$ Preset for .NE. condition!
00128 +A 09a0 b6 6a A LDA YREG1$+1
00128 +A 09a2 b1 01 A CMP (ZERO)+1
00128 +A 09a4 26 08 09ae BNE .00089 Branch if LS half is .NE.
00128 +A 09a6 b6 69 A LDA YREG1$
00128 +A 09a8 b1 00 A CMP (ZERO)
M6805 Portable Cross Assembler 0.05 test1.s Page 37
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00128 +A 09aa 26 02 09ae BNE .00089 Branch if MS half is .NE.
00128 +A 09ac 3f bd A CLR TESTA$ Set for .EQ. condition!
00128 +A 09ae b6 b9 A .00089 LDA TEMPA$
00128 +A 09b0 3d bd A TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
00129 MACRO INV CPYR LOW !-------------------------
00129 + IFEQ NARG-1
00129 +A 09b2 b7 b9 A STA TEMPA$
00129 +A 09b4 10 bd A BSET 0,TESTA$ Preset for .NE. condition!
00129 +A 09b6 b6 6a A LDA YREG1$+1
00129 +A 09b8 b1 51 A CMP (LOW)+1
00129 +A 09ba 26 08 09c4 BNE .00090 Branch if LS half is .NE.
00129 +A 09bc b6 69 A LDA YREG1$
00129 +A 09be b1 50 A CMP (LOW)
00129 +A 09c0 26 02 09c4 BNE .00090 Branch if MS half is .NE.
00129 +A 09c2 3f bd A CLR TESTA$ Set for .EQ. condition!
00129 +A 09c4 b6 b9 A .00090 LDA TEMPA$
00129 +A 09c6 3d bd A TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
00130 MACRO INV CPYR HIGH !-------------------------
00130 + IFEQ NARG-1
00130 +A 09c8 b7 b9 A STA TEMPA$
00130 +A 09ca 10 bd A BSET 0,TESTA$ Preset for .NE. condition!
00130 +A 09cc b6 6a A LDA YREG1$+1
00130 +A 09ce c1 1eff A CMP (HIGH)+1
00130 +A 09d1 26 09 09dc BNE .00091 Branch if LS half is .NE.
00130 +A 09d3 b6 69 A LDA YREG1$
00130 +A 09d5 c1 1efe A CMP (HIGH)
00130 +A 09d8 26 02 09dc BNE .00091 Branch if MS half is .NE.
00130 +A 09da 3f bd A CLR TESTA$ Set for .EQ. condition!
00130 +A 09dc b6 b9 A .00091 LDA TEMPA$
00130 +A 09de 3d bd A TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
00131 MACRO INV CPYR #,0 !-------------------------
00131 + IFEQ NARG-1
00131 + ENDC
00131 + IFEQ NARG-2
00131 + IFC '#','#'
00131 + IFEQ 0
00131 + IFEQ YREG1$!.$FF00
00131 +A 09e0 3d 6a A TST YREG1$+1
00131 +A 09e2 26 02 09e6 BNE .00092 Branch if LS half is .NE.
00131 +A 09e4 3d 69 A TST YREG1$
00131 +A 09e6 09e6 A .00092 EQU *
00132 MACRO INV CPYR #,LOW !-------------------------
00132 + IFEQ NARG-1
00132 + ENDC
00132 + IFEQ NARG-2
00132 + IFC '#','#'
00132 + IFEQ LOW
00132 + ENDC
00132 +A 09e6 b7 b9 A STA TEMPA$
00132 +A 09e8 10 bd A BSET 0,TESTA$ Preset for .NE. condition!
00132 +A 09ea b6 6a A LDA YREG1$+1
00132 + IFNE (LOW)!.$FF
M6805 Portable Cross Assembler 0.05 test1.s Page 38
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00132 +A 09ec a1 50 A CMP #(LOW)!.$FF
00132 + ENDC
00132 +A 09ee 26 06 09f6 BNE .00093 Branch if LS half is .NE.
00132 +A 09f0 b6 69 A LDA YREG1$
00132 + IFNE (LOW)!>8
00132 + ENDC
00132 +A 09f2 26 02 09f6 BNE .00093 Branch if MS half is .NE.
00132 +A 09f4 3f bd A CLR TESTA$ Set for .EQ. condition!
00132 +A 09f6 b6 b9 A .00093 LDA TEMPA$
00132 +A 09f8 3d bd A TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
00133 MACRO INV CPYR #,HIGH !-------------------------
00133 + IFEQ NARG-1
00133 + ENDC
00133 + IFEQ NARG-2
00133 + IFC '#','#'
00133 + IFEQ HIGH
00133 + ENDC
00133 +A 09fa b7 b9 A STA TEMPA$
00133 +A 09fc 10 bd A BSET 0,TESTA$ Preset for .NE. condition!
00133 +A 09fe b6 6a A LDA YREG1$+1
00133 + IFNE (HIGH)!.$FF
00133 +A 0a00 a1 fe A CMP #(HIGH)!.$FF
00133 + ENDC
00133 +A 0a02 26 08 0a0c BNE .00094 Branch if LS half is .NE.
00133 +A 0a04 b6 69 A LDA YREG1$
00133 + IFNE (HIGH)!>8
00133 +A 0a06 a1 1e A CMP #(HIGH)!>8
00133 + ENDC
00133 +A 0a08 26 02 0a0c BNE .00094 Branch if MS half is .NE.
00133 +A 0a0a 3f bd A CLR TESTA$ Set for .EQ. condition!
00133 +A 0a0c b6 b9 A .00094 LDA TEMPA$
00133 +A 0a0e 3d bd A TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
00134 MACRO INV CPYR #,HIGH0 !-------------------------
00134 + IFEQ NARG-1
00134 + ENDC
00134 + IFEQ NARG-2
00134 + IFC '#','#'
00134 + IFEQ HIGH0
00134 + ENDC
00134 +A 0a10 b7 b9 A STA TEMPA$
00134 +A 0a12 10 bd A BSET 0,TESTA$ Preset for .NE. condition!
00134 +A 0a14 b6 6a A LDA YREG1$+1
00134 + IFNE (HIGH0)!.$FF
00134 + ENDC
00134 +A 0a16 26 08 0a20 BNE .00095 Branch if LS half is .NE.
00134 +A 0a18 b6 69 A LDA YREG1$
00134 + IFNE (HIGH0)!>8
00134 +A 0a1a a1 1e A CMP #(HIGH0)!>8
00134 + ENDC
00134 +A 0a1c 26 02 0a20 BNE .00095 Branch if MS half is .NE.
00134 +A 0a1e 3f bd A CLR TESTA$ Set for .EQ. condition!
00134 +A 0a20 b6 b9 A .00095 LDA TEMPA$
M6805 Portable Cross Assembler 0.05 test1.s Page 39
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00134 +A 0a22 3d bd A TST TESTA$ Set proper Z-bit (.EQ. or .NE.)!
00135
00136 * @@@@@@@@ DEC tests start here
00137 MACRO INV DEC.B LOW !-------------------------
00137 + IFEQ NARG-1
00137 + IFEQ (LOW)!.$FF00
00137 +A 0a24 3a 50 A DEC LOW
00138 MACRO INV DEC.B #,5,LOW !-------------------------
00138 + IFEQ NARG-1
00138 + ENDC
00138 + IFEQ NARG-2
00138 + ENDC
00138 + IFEQ NARG-3
00138 + IFC '#','#'
00138 +A 0a26 b7 b9 A STA TEMPA$
00138 +A 0a28 b6 50 A LDA LOW
00138 +A 0a2a a0 05 A SUB #5
00138 +A 0a2c b7 50 A STA LOW
00138 + IFEQ (LOW)!.$FF00
00138 +A 0a2e b6 b9 A LDA TEMPA$
00138 +A 0a30 3d 50 A TST LOW
00139 MACRO INV DEC.B CNTL,LOW !------------------------
00139 + IFEQ NARG-1
00139 + ENDC
00139 + IFEQ NARG-2
00139 +A 0a32 b7 b9 A STA TEMPA$
00139 +A 0a34 b6 50 A LDA LOW
00139 +A 0a36 b0 52 A SUB CNTL
00139 +A 0a38 b7 50 A STA LOW
00139 + IFEQ (LOW)!.$FF00
00139 +A 0a3a b6 b9 A LDA TEMPA$
00139 +A 0a3c 3d 50 A TST LOW
00140 MACRO INV DEC.B CNTH,LOW !------------------------
00140 + IFEQ NARG-1
00140 + ENDC
00140 + IFEQ NARG-2
00140 +A 0a3e b7 b9 A STA TEMPA$
00140 +A 0a40 b6 50 A LDA LOW
00140 +A 0a42 c0 1efc A SUB CNTH
00140 +A 0a45 b7 50 A STA LOW
00140 + IFEQ (LOW)!.$FF00
00140 +A 0a47 b6 b9 A LDA TEMPA$
00140 +A 0a49 3d 50 A TST LOW
00141
00142 MACRO INV DEC.W LOW !-------------------------
00142 + IFEQ NARG-1
00142 +A 0a4b b7 b9 A STA TEMPA$
00142 +A 0a4d b6 51 A LDA (LOW)+1
00142 +A 0a4f a0 01 A SUB #1
00142 +A 0a51 b7 51 A STA (LOW)+1
00142 +A 0a53 b6 50 A LDA LOW
00142 +A 0a55 a2 00 A SBC #0
M6805 Portable Cross Assembler 0.05 test1.s Page 40
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00142 +A 0a57 b7 50 A STA LOW
00142 +A 0a59 ba 51 A ORA (LOW)+1
00142 +A 0a5b b7 bd A STA TESTA$
00142 +A 0a5d b6 b9 A LDA TEMPA$
00142 +A 0a5f 3d bd A TST TESTA$
00143 MACRO INV DEC.W #,5,LOW !-------------------------
00143 + IFEQ NARG-1
00143 + ENDC
00143 + IFEQ NARG-2
00143 + ENDC
00143 + IFEQ NARG-3
00143 + IFC '#','#'
00143 +A 0a61 b7 b9 A STA TEMPA$
00143 +A 0a63 b6 51 A LDA (LOW)+1
00143 +A 0a65 a0 05 A SUB #(5)!.$FF
00143 +A 0a67 b7 51 A STA (LOW)+1
00143 +A 0a69 b6 50 A LDA LOW
00143 +A 0a6b a2 00 A SBC #(5)!>8
00143 +A 0a6d b7 50 A STA LOW
00143 +A 0a6f ba 51 A ORA (LOW)+1
00143 +A 0a71 b7 bd A STA TESTA$
00143 +A 0a73 b6 b9 A LDA TEMPA$
00143 +A 0a75 3d bd A TST TESTA$
00144 MACRO INV DEC.W CNTL,LOW !------------------------
00144 + IFEQ NARG-1
00144 + ENDC
00144 + IFEQ NARG-2
00144 +A 0a77 b7 b9 A STA TEMPA$
00144 +A 0a79 b6 51 A LDA (LOW)+1
00144 +A 0a7b b0 53 A SUB (CNTL)+1
00144 +A 0a7d b7 51 A STA (LOW)+1
00144 +A 0a7f b6 50 A LDA LOW
00144 +A 0a81 b2 52 A SBC CNTL
00144 +A 0a83 b7 50 A STA LOW
00144 +A 0a85 ba 51 A ORA (LOW)+1
00144 +A 0a87 b7 bd A STA TESTA$
00144 +A 0a89 b6 b9 A LDA TEMPA$
00144 +A 0a8b 3d bd A TST TESTA$
00145 MACRO INV DEC.W CNTH,LOW !------------------------
00145 + IFEQ NARG-1
00145 + ENDC
00145 + IFEQ NARG-2
00145 +A 0a8d b7 b9 A STA TEMPA$
00145 +A 0a8f b6 51 A LDA (LOW)+1
00145 +A 0a91 c0 1efd A SUB (CNTH)+1
00145 +A 0a94 b7 51 A STA (LOW)+1
00145 +A 0a96 b6 50 A LDA LOW
00145 +A 0a98 c2 1efc A SBC CNTH
00145 +A 0a9b b7 50 A STA LOW
00145 +A 0a9d ba 51 A ORA (LOW)+1
00145 +A 0a9f b7 bd A STA TESTA$
00145 +A 0aa1 b6 b9 A LDA TEMPA$
M6805 Portable Cross Assembler 0.05 test1.s Page 41
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00145 +A 0aa3 3d bd A TST TESTA$
00146
00147 MACRO INV INC.B LOW !-------------------------
00147 + IFEQ NARG-1
00147 + IFEQ (LOW)!.$FF00
00147 +A 0aa5 3c 50 A INC LOW
00148 MACRO INV INC.B #,5,LOW !-------------------------
00148 + IFEQ NARG-1
00148 + ENDC
00148 + IFEQ NARG-2
00148 + ENDC
00148 + IFEQ NARG-3
00148 + IFC '#','#'
00148 +A 0aa7 b7 b9 A STA TEMPA$
00148 +A 0aa9 b6 50 A LDA LOW
00148 +A 0aab ab 05 A ADD #5
00148 +A 0aad b7 50 A STA LOW
00148 + IFEQ (LOW)!.$FF00
00148 +A 0aaf b6 b9 A LDA TEMPA$
00148 +A 0ab1 3d 50 A TST LOW
00149 MACRO INV INC.B CNTL,LOW !------------------------
00149 + IFEQ NARG-1
00149 + ENDC
00149 + IFEQ NARG-2
00149 +A 0ab3 b7 b9 A STA TEMPA$
00149 +A 0ab5 b6 50 A LDA LOW
00149 +A 0ab7 bb 52 A ADD CNTL
00149 +A 0ab9 b7 50 A STA LOW
00149 + IFEQ (LOW)!.$FF00
00149 +A 0abb b6 b9 A LDA TEMPA$
00149 +A 0abd 3d 50 A TST LOW
00150 MACRO INV INC.B CNTH,LOW !------------------------
00150 + IFEQ NARG-1
00150 + ENDC
00150 + IFEQ NARG-2
00150 +A 0abf b7 b9 A STA TEMPA$
00150 +A 0ac1 b6 50 A LDA LOW
00150 +A 0ac3 cb 1efc A ADD CNTH
00150 +A 0ac6 b7 50 A STA LOW
00150 + IFEQ (LOW)!.$FF00
00150 +A 0ac8 b6 b9 A LDA TEMPA$
00150 +A 0aca 3d 50 A TST LOW
00151
00152 MACRO INV INC.W LOW !-------------------------
00152 + IFEQ NARG-1
00152 + IFEQ (LOW)!.$FF00
00152 +A 0acc 3c 51 A INC (LOW)+1
00152 +A 0ace 26 02 0ad2 BNE .00108
00152 +A 0ad0 3c 50 A INC LOW
00152 +A 0ad2 0ad2 A .00108 EQU *
00153 MACRO INV INC.W #,5,LOW !-------------------------
00153 + IFEQ NARG-1
M6805 Portable Cross Assembler 0.05 test1.s Page 42
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00153 + ENDC
00153 + IFEQ NARG-2
00153 + ENDC
00153 + IFEQ NARG-3
00153 + IFC '#','#'
00153 +A 0ad2 b7 b9 A STA TEMPA$
00153 +A 0ad4 b6 51 A LDA (LOW)+1
00153 +A 0ad6 ab 05 A ADD #(5)!.$FF
00153 +A 0ad8 b7 51 A STA (LOW)+1
00153 +A 0ada b6 50 A LDA LOW
00153 +A 0adc a9 00 A ADC #(5)!>8
00153 +A 0ade b7 50 A STA LOW
00153 +A 0ae0 ba 51 A ORA (LOW)+1
00153 +A 0ae2 b7 bd A STA TESTA$
00153 +A 0ae4 b6 b9 A LDA TEMPA$
00153 +A 0ae6 3d bd A TST TESTA$
00154 MACRO INV INC.W CNTL,LOW !------------------------
00154 + IFEQ NARG-1
00154 + ENDC
00154 + IFEQ NARG-2
00154 +A 0ae8 b7 b9 A STA TEMPA$
00154 +A 0aea b6 51 A LDA (LOW)+1
00154 +A 0aec bb 53 A ADD (CNTL)+1
00154 +A 0aee b7 51 A STA (LOW)+1
00154 +A 0af0 b6 50 A LDA LOW
00154 +A 0af2 b9 52 A ADC CNTL
00154 +A 0af4 b7 50 A STA LOW
00154 +A 0af6 ba 51 A ORA (LOW)+1
00154 +A 0af8 b7 bd A STA TESTA$
00154 +A 0afa b6 b9 A LDA TEMPA$
00154 +A 0afc 3d bd A TST TESTA$
00155 MACRO INV INC.W CNTH,LOW !------------------------
00155 + IFEQ NARG-1
00155 + ENDC
00155 + IFEQ NARG-2
00155 +A 0afe b7 b9 A STA TEMPA$
00155 +A 0b00 b6 51 A LDA (LOW)+1
00155 +A 0b02 cb 1efd A ADD (CNTH)+1
00155 +A 0b05 b7 51 A STA (LOW)+1
00155 +A 0b07 b6 50 A LDA LOW
00155 +A 0b09 c9 1efc A ADC CNTH
00155 +A 0b0c b7 50 A STA LOW
00155 +A 0b0e ba 51 A ORA (LOW)+1
00155 +A 0b10 b7 bd A STA TESTA$
00155 +A 0b12 b6 b9 A LDA TEMPA$
00155 +A 0b14 3d bd A TST TESTA$
00156
00157 * @@@@@@@@ MOV tests start here
00158 MACRO INV MOV.B #,0,LOW !-------------------------
00158 + IFEQ NARG-2
00158 + ENDC
00158 + IFEQ NARG-3
M6805 Portable Cross Assembler 0.05 test1.s Page 43
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00158 + IFC '#','#'
00158 + IFEQ (LOW)!.$FF00
00158 + IFEQ 0
00158 +A 0b16 3f 50 A CLR LOW
00159 MACRO INV MOV.B #,5,LOW !-------------------------
00159 + IFEQ NARG-2
00159 + ENDC
00159 + IFEQ NARG-3
00159 + IFC '#','#'
00159 + IFEQ (LOW)!.$FF00
00159 + IFEQ 5
00159 + ENDC
00159 + ENDC
00159 +A 0b18 b7 b9 A STA TEMPA$
00159 + IFEQ 5
00159 + ENDC
00159 + IFNE 5
00159 +A 0b1a a6 05 A LDA #5
00159 + ENDC
00159 +A 0b1c b7 50 A STA LOW
00159 + IFEQ (LOW)!.$FF00
00159 +A 0b1e b6 b9 A LDA TEMPA$
00159 +A 0b20 3d 50 A TST LOW
00160 MACRO INV MOV.B CNTL,LOW !------------------------
00160 + IFEQ NARG-2
00160 +A 0b22 b7 b9 A STA TEMPA$
00160 +A 0b24 b6 52 A LDA CNTL
00160 +A 0b26 b7 50 A STA LOW
00160 + IFEQ (LOW)!.$FF00
00160 +A 0b28 b6 b9 A LDA TEMPA$
00160 +A 0b2a 3d 50 A TST LOW
00161 MACRO INV MOV.B CNTH,LOW !------------------------
00161 + IFEQ NARG-2
00161 +A 0b2c b7 b9 A STA TEMPA$
00161 +A 0b2e c6 1efc A LDA CNTH
00161 +A 0b31 b7 50 A STA LOW
00161 + IFEQ (LOW)!.$FF00
00161 +A 0b33 b6 b9 A LDA TEMPA$
00161 +A 0b35 3d 50 A TST LOW
00162 MACRO INV MOV.B #,0,HIGH !------------------------
00162 + IFEQ NARG-2
00162 + ENDC
00162 + IFEQ NARG-3
00162 + IFC '#','#'
00162 + IFEQ (HIGH)!.$FF00
00162 + ENDC
00162 +A 0b37 b7 b9 A STA TEMPA$
00162 + IFEQ 0
00162 +A 0b39 4f CLRA
00162 + ENDC
00162 + IFNE 0
00162 + ENDC
M6805 Portable Cross Assembler 0.05 test1.s Page 44
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00162 +A 0b3a c7 1efe A STA HIGH
00162 + IFEQ (HIGH)!.$FF00
00162 + ENDC
00162 + IFNE (HIGH)!.$FF00
00162 +A 0b3d b7 bd A STA TESTA$
00162 +A 0b3f b6 b9 A LDA TEMPA$
00162 +A 0b41 3d bd A TST TESTA$
00163 MACRO INV MOV.B #,5,HIGH !------------------------
00163 + IFEQ NARG-2
00163 + ENDC
00163 + IFEQ NARG-3
00163 + IFC '#','#'
00163 + IFEQ (HIGH)!.$FF00
00163 + ENDC
00163 +A 0b43 b7 b9 A STA TEMPA$
00163 + IFEQ 5
00163 + ENDC
00163 + IFNE 5
00163 +A 0b45 a6 05 A LDA #5
00163 + ENDC
00163 +A 0b47 c7 1efe A STA HIGH
00163 + IFEQ (HIGH)!.$FF00
00163 + ENDC
00163 + IFNE (HIGH)!.$FF00
00163 +A 0b4a b7 bd A STA TESTA$
00163 +A 0b4c b6 b9 A LDA TEMPA$
00163 +A 0b4e 3d bd A TST TESTA$
00164 MACRO INV MOV.B CNTL,HIGH !-----------------------
00164 + IFEQ NARG-2
00164 +A 0b50 b7 b9 A STA TEMPA$
00164 +A 0b52 b6 52 A LDA CNTL
00164 +A 0b54 c7 1efe A STA HIGH
00164 + IFEQ (HIGH)!.$FF00
00164 + ENDC
00164 + IFNE (HIGH)!.$FF00
00164 + IFEQ (CNTL)!.$FF00
00164 +A 0b57 b6 b9 A LDA TEMPA$
00164 +A 0b59 3d 52 A TST CNTL
00165 MACRO INV MOV.B CNTH,HIGH !-----------------------
00165 + IFEQ NARG-2
00165 +A 0b5b b7 b9 A STA TEMPA$
00165 +A 0b5d c6 1efc A LDA CNTH
00165 +A 0b60 c7 1efe A STA HIGH
00165 + IFEQ (HIGH)!.$FF00
00165 + ENDC
00165 + IFNE (HIGH)!.$FF00
00165 + IFEQ (CNTH)!.$FF00
00165 + ENDC
00165 + IFNE (CNTH)!.$FF00
00165 +A 0b63 b7 bd A STA TESTA$
00165 +A 0b65 b6 b9 A LDA TEMPA$
00165 +A 0b67 3d bd A TST TESTA$
M6805 Portable Cross Assembler 0.05 test1.s Page 45
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00166
00167 MACRO INV MOV.W #,0,LOW !-------------------------
00167 + IFEQ NARG-2
00167 + ENDC
00167 + IFEQ NARG-3
00167 + IFC '#','#'
00167 + IFEQ ((LOW)+1)!.$FF00
00167 + IFEQ 0
00167 +A 0b69 3f 50 A CLR LOW
00167 +A 0b6b 3f 51 A CLR LOW+1
00168 MACRO INV MOV.W #,5,LOW !-------------------------
00168 + IFEQ NARG-2
00168 + ENDC
00168 + IFEQ NARG-3
00168 + IFC '#','#'
00168 + IFEQ ((LOW)+1)!.$FF00
00168 + IFEQ 5
00168 + ENDC
00168 + ENDC
00168 +A 0b6d b7 b9 A STA TEMPA$
00168 + IFEQ (5)!.$00FF
00168 + ENDC
00168 + IFNE (5)!.$00FF
00168 +A 0b6f a6 05 A LDA #(5)!.$00FF
00168 + ENDC
00168 +A 0b71 b7 51 A STA (LOW)+1
00168 + IFEQ (5)!>8
00168 + IFNE (5)!.$00FF
00168 +A 0b73 4f CLRA
00168 + ENDC
00168 + ENDC
00168 + IFNE (5)!>8
00168 + ENDC
00168 +A 0b74 b7 50 A STA LOW
00168 + IFEQ (LOW)!.$FF00
00168 +A 0b76 b6 b9 A LDA TEMPA$
00168 +A 0b78 3d 50 A TST LOW
00169 MACRO INV MOV.W #,CNTL,LOW !----------------------
00169 + IFEQ NARG-2
00169 + ENDC
00169 + IFEQ NARG-3
00169 + IFC '#','#'
00169 + IFEQ ((LOW)+1)!.$FF00
00169 + IFEQ CNTL
00169 + ENDC
00169 + ENDC
00169 +A 0b7a b7 b9 A STA TEMPA$
00169 + IFEQ (CNTL)!.$00FF
00169 + ENDC
00169 + IFNE (CNTL)!.$00FF
00169 +A 0b7c a6 52 A LDA #(CNTL)!.$00FF
00169 + ENDC
M6805 Portable Cross Assembler 0.05 test1.s Page 46
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00169 +A 0b7e b7 51 A STA (LOW)+1
00169 + IFEQ (CNTL)!>8
00169 + IFNE (CNTL)!.$00FF
00169 +A 0b80 4f CLRA
00169 + ENDC
00169 + ENDC
00169 + IFNE (CNTL)!>8
00169 + ENDC
00169 +A 0b81 b7 50 A STA LOW
00169 + IFEQ (LOW)!.$FF00
00169 +A 0b83 b6 b9 A LDA TEMPA$
00169 +A 0b85 3d 50 A TST LOW
00170 MACRO INV MOV.W #,CNTH,LOW !----------------------
00170 + IFEQ NARG-2
00170 + ENDC
00170 + IFEQ NARG-3
00170 + IFC '#','#'
00170 + IFEQ ((LOW)+1)!.$FF00
00170 + IFEQ CNTH
00170 + ENDC
00170 + ENDC
00170 +A 0b87 b7 b9 A STA TEMPA$
00170 + IFEQ (CNTH)!.$00FF
00170 + ENDC
00170 + IFNE (CNTH)!.$00FF
00170 +A 0b89 a6 fc A LDA #(CNTH)!.$00FF
00170 + ENDC
00170 +A 0b8b b7 51 A STA (LOW)+1
00170 + IFEQ (CNTH)!>8
00170 + ENDC
00170 + IFNE (CNTH)!>8
00170 +A 0b8d a6 1e A LDA #(CNTH)!>8
00170 + ENDC
00170 +A 0b8f b7 50 A STA LOW
00170 + IFEQ (LOW)!.$FF00
00170 +A 0b91 b6 b9 A LDA TEMPA$
00170 +A 0b93 3d 50 A TST LOW
00171 MACRO INV MOV.W CNTL,LOW !------------------------
00171 + IFEQ NARG-2
00171 +A 0b95 b7 b9 A STA TEMPA$
00171 +A 0b97 b6 53 A LDA (CNTL)+1
00171 +A 0b99 b7 51 A STA (LOW)+1
00171 +A 0b9b b6 52 A LDA CNTL
00171 +A 0b9d b7 50 A STA LOW
00171 + IFEQ (LOW)!.$FF00
00171 +A 0b9f b6 b9 A LDA TEMPA$
00171 +A 0ba1 3d 50 A TST LOW
00172 MACRO INV MOV.W CNTH,LOW !------------------------
00172 + IFEQ NARG-2
00172 +A 0ba3 b7 b9 A STA TEMPA$
00172 +A 0ba5 c6 1efd A LDA (CNTH)+1
00172 +A 0ba8 b7 51 A STA (LOW)+1
M6805 Portable Cross Assembler 0.05 test1.s Page 47
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00172 +A 0baa c6 1efc A LDA CNTH
00172 +A 0bad b7 50 A STA LOW
00172 + IFEQ (LOW)!.$FF00
00172 +A 0baf b6 b9 A LDA TEMPA$
00172 +A 0bb1 3d 50 A TST LOW
00173 MACRO INV MOV.W #,0,HIGH !------------------------
00173 + IFEQ NARG-2
00173 + ENDC
00173 + IFEQ NARG-3
00173 + IFC '#','#'
00173 + IFEQ ((HIGH)+1)!.$FF00
00173 + ENDC
00173 +A 0bb3 b7 b9 A STA TEMPA$
00173 + IFEQ (0)!.$00FF
00173 +A 0bb5 4f CLRA
00173 + ENDC
00173 + IFNE (0)!.$00FF
00173 + ENDC
00173 +A 0bb6 c7 1eff A STA (HIGH)+1
00173 + IFEQ (0)!>8
00173 + IFNE (0)!.$00FF
00173 + ENDC
00173 + ENDC
00173 + IFNE (0)!>8
00173 + ENDC
00173 +A 0bb9 c7 1efe A STA HIGH
00173 + IFEQ (HIGH)!.$FF00
00173 + ENDC
00173 + IFNE (HIGH)!.$FF00
00173 +A 0bbc b7 bd A STA TESTA$
00173 +A 0bbe b6 b9 A LDA TEMPA$
00173 +A 0bc0 3d bd A TST TESTA$
00174 MACRO INV MOV.W #,5,HIGH !------------------------
00174 + IFEQ NARG-2
00174 + ENDC
00174 + IFEQ NARG-3
00174 + IFC '#','#'
00174 + IFEQ ((HIGH)+1)!.$FF00
00174 + ENDC
00174 +A 0bc2 b7 b9 A STA TEMPA$
00174 + IFEQ (5)!.$00FF
00174 + ENDC
00174 + IFNE (5)!.$00FF
00174 +A 0bc4 a6 05 A LDA #(5)!.$00FF
00174 + ENDC
00174 +A 0bc6 c7 1eff A STA (HIGH)+1
00174 + IFEQ (5)!>8
00174 + IFNE (5)!.$00FF
00174 +A 0bc9 4f CLRA
00174 + ENDC
00174 + ENDC
00174 + IFNE (5)!>8
M6805 Portable Cross Assembler 0.05 test1.s Page 48
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00174 + ENDC
00174 +A 0bca c7 1efe A STA HIGH
00174 + IFEQ (HIGH)!.$FF00
00174 + ENDC
00174 + IFNE (HIGH)!.$FF00
00174 +A 0bcd b7 bd A STA TESTA$
00174 +A 0bcf b6 b9 A LDA TEMPA$
00174 +A 0bd1 3d bd A TST TESTA$
00175 MACRO INV MOV.W #,CNTL,HIGH !---------------------
00175 + IFEQ NARG-2
00175 + ENDC
00175 + IFEQ NARG-3
00175 + IFC '#','#'
00175 + IFEQ ((HIGH)+1)!.$FF00
00175 + ENDC
00175 +A 0bd3 b7 b9 A STA TEMPA$
00175 + IFEQ (CNTL)!.$00FF
00175 + ENDC
00175 + IFNE (CNTL)!.$00FF
00175 +A 0bd5 a6 52 A LDA #(CNTL)!.$00FF
00175 + ENDC
00175 +A 0bd7 c7 1eff A STA (HIGH)+1
00175 + IFEQ (CNTL)!>8
00175 + IFNE (CNTL)!.$00FF
00175 +A 0bda 4f CLRA
00175 + ENDC
00175 + ENDC
00175 + IFNE (CNTL)!>8
00175 + ENDC
00175 +A 0bdb c7 1efe A STA HIGH
00175 + IFEQ (HIGH)!.$FF00
00175 + ENDC
00175 + IFNE (HIGH)!.$FF00
00175 +A 0bde b7 bd A STA TESTA$
00175 +A 0be0 b6 b9 A LDA TEMPA$
00175 +A 0be2 3d bd A TST TESTA$
00176 MACRO INV MOV.W #,CNTH,HIGH !---------------------
00176 + IFEQ NARG-2
00176 + ENDC
00176 + IFEQ NARG-3
00176 + IFC '#','#'
00176 + IFEQ ((HIGH)+1)!.$FF00
00176 + ENDC
00176 +A 0be4 b7 b9 A STA TEMPA$
00176 + IFEQ (CNTH)!.$00FF
00176 + ENDC
00176 + IFNE (CNTH)!.$00FF
00176 +A 0be6 a6 fc A LDA #(CNTH)!.$00FF
00176 + ENDC
00176 +A 0be8 c7 1eff A STA (HIGH)+1
00176 + IFEQ (CNTH)!>8
00176 + ENDC
M6805 Portable Cross Assembler 0.05 test1.s Page 49
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00176 + IFNE (CNTH)!>8
00176 +A 0beb a6 1e A LDA #(CNTH)!>8
00176 + ENDC
00176 +A 0bed c7 1efe A STA HIGH
00176 + IFEQ (HIGH)!.$FF00
00176 + ENDC
00176 + IFNE (HIGH)!.$FF00
00176 +A 0bf0 b7 bd A STA TESTA$
00176 +A 0bf2 b6 b9 A LDA TEMPA$
00176 +A 0bf4 3d bd A TST TESTA$
00177 MACRO INV MOV.W CNTL,HIGH !-----------------------
00177 + IFEQ NARG-2
00177 +A 0bf6 b7 b9 A STA TEMPA$
00177 +A 0bf8 b6 53 A LDA (CNTL)+1
00177 +A 0bfa c7 1eff A STA (HIGH)+1
00177 +A 0bfd b6 52 A LDA CNTL
00177 +A 0bff c7 1efe A STA HIGH
00177 + IFEQ (HIGH)!.$FF00
00177 + ENDC
00177 + IFNE (HIGH)!.$FF00
00177 + IFEQ (CNTL)!.$FF00
00177 +A 0c02 b6 b9 A LDA TEMPA$
00177 +A 0c04 3d 52 A TST CNTL
00178 MACRO INV MOV.W CNTH,HIGH !-----------------------
00178 + IFEQ NARG-2
00178 +A 0c06 b7 b9 A STA TEMPA$
00178 +A 0c08 c6 1efd A LDA (CNTH)+1
00178 +A 0c0b c7 1eff A STA (HIGH)+1
00178 +A 0c0e c6 1efc A LDA CNTH
00178 +A 0c11 c7 1efe A STA HIGH
00178 + IFEQ (HIGH)!.$FF00
00178 + ENDC
00178 + IFNE (HIGH)!.$FF00
00178 + IFEQ (CNTH)!.$FF00
00178 + ENDC
00178 + IFNE (CNTH)!.$FF00
00178 +A 0c14 b7 bd A STA TESTA$
00178 +A 0c16 b6 b9 A LDA TEMPA$
00178 +A 0c18 3d bd A TST TESTA$
00179
00180 * @@@@@@@@ MOVE tests start here
00181 MACRO INV MOVE #,.RAMSBR$,#,RAMSBR$,#,RAMSZ$ !---
00181 + IFNE NARG-6
00181 + ENDC
00181 + IFC '#','#' ! If all immediate operands (#) and move
00181 + IFC '#','#' ! count <=256, use short form!
00181 + IFC '#','#'
00181 + IFLE RAMSZ$-256 ! No subr. calls!
00181 +A 0c1a b7 b9 A STA TEMPA$
00181 +A 0c1c bf ba A STX TEMPX$
00181 +A 0c1e ae 10 A LDX #(RAMSZ$)
00181 +A 0c20 d6 03ff A .00132 LDA (.RAMSBR$)-1,x
M6805 Portable Cross Assembler 0.05 test1.s Page 50
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00181 +A 0c23 e75f STA (RAMSBR$)-1,x
00181 +A 0c25 5a DEX
00181 +A 0c26 26 f8 0c20 BNE .00132
00181 +A 0c28 b6 b9 A LDA TEMPA$
00181 +A 0c2a be ba A LDX TEMPX$
00182 MACRO INV MOVE #,.RAMSBR$,#,RAMSBR$,,CNTL !------
00182 + IFNE NARG-6
00182 + ENDC
00182 + IFC '','#' ! If all immediate operands (#) and move
00182 + ENDC
00182 +A 0c2c b7 b9 A STA TEMPA$
00182 +A 0c2e bf ba A STX TEMPX$
00182 +A 0c30 b6 61 A LDA XREG1$
00182 +A 0c32 b7 bb A STA TEMPXR$
00182 +A 0c34 b6 62 A LDA XREG1$+1
00182 +A 0c36 b7 bc A STA TEMPXR$+1
00182 + IFC '#','#' ! immediate type 'from' address?
00182 +A 0c38 a6 00 A LDA #(.RAMSBR$)!.$FF
00182 +A 0c3a b7 62 A STA XREG1$+1 ! Set XREG1$ = 'from' address
00182 +A 0c3c a6 04 A LDA #(.RAMSBR$)!>8
00182 +A 0c3e b7 61 A STA XREG1$
00182 + ENDC
00182 + IFNC '#','#' ! not immediate type 'from' address?
00182 + ENDC
00182 + IFC '#','#' ! immediate type 'to' address?
00182 +A 0c40 a6 60 A LDA #(RAMSBR$)!.$FF
00182 +A 0c42 b7 66 A STA XREG2$+1 ! Set XREG2$ = 'to' address
00182 +A 0c44 a6 00 A LDA #(RAMSBR$)!>8
00182 +A 0c46 b7 65 A STA XREG2$
00182 + ENDC
00182 + IFNC '#','#' ! not immediate type 'to' address?
00182 + ENDC
00182 + IFC '','#' ! immediate type length?
00182 + ENDC
00182 + IFNC '','#' ! nonimmediate type length
00182 +A 0c48 b6 52 A LDA (CNTL)!.$00FF
00182 +A 0c4a b7 bf A STA LENGTH$+1
00182 +A 0c4c b6 00 A LDA (CNTL)!>8
00182 +A 0c4e b7 be A STA LENGTH$
00182 +A 0c50 bd 60 A .00135 JSR LDAXREG
00182 +A 0c52 bd 64 A JSR STAXREG
00182 + IFEQ XREG1$!.$FF00
00182 +A 0c54 3c 62 A INC XREG1$+1
00182 +A 0c56 26 02 0c5a BNE .00136
00182 +A 0c58 3c 61 A INC XREG1$
00182 +A 0c5a 3c 66 A .00136 INC XREG2$+1
00182 +A 0c5c 26 02 0c60 BNE .00137
00182 +A 0c5e 3c 65 A INC XREG2$
00182 +A 0c60 0c60 A .00137 EQU *
00182 + ENDC
00182 + IFNE XREG1$!.$FF00
00182 + ENDC
M6805 Portable Cross Assembler 0.05 test1.s Page 51
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00182 +A 0c60 b6 bf A LDA LENGTH$+1
00182 +A 0c62 a0 01 A SUB #1
00182 +A 0c64 b7 bf A STA LENGTH$+1
00182 +A 0c66 b6 be A LDA LENGTH$
00182 +A 0c68 a2 00 A SBC #0
00182 +A 0c6a b7 be A STA LENGTH$
00182 +A 0c6c ba bf A ORA LENGTH$+1
00182 +A 0c6e 26 e0 0c50 BNE .00135
00182 +A 0c70 b6 bb A LDA TEMPXR$
00182 +A 0c72 b7 61 A STA XREG1$
00182 +A 0c74 b7 65 A STA XREG2$
00182 +A 0c76 b6 bc A LDA TEMPXR$+1
00182 +A 0c78 b7 62 A STA XREG1$+1
00182 +A 0c7a b7 66 A STA XREG2$+1
00182 +A 0c7c b6 b9 A LDA TEMPA$
00182 +A 0c7e be ba A LDX TEMPX$
00183 MACRO INV MOVE #,.RAMSBR$,,LOW,#,RAMSZ$ !--------
00183 + IFNE NARG-6
00183 + ENDC
00183 + IFC '#','#' ! If all immediate operands (#) and move
00183 + IFC '','#' ! count <=256, use short form!
00183 + ENDC
00183 + ENDC
00183 +A 0c80 b7 b9 A STA TEMPA$
00183 +A 0c82 bf ba A STX TEMPX$
00183 +A 0c84 b6 61 A LDA XREG1$
00183 +A 0c86 b7 bb A STA TEMPXR$
00183 +A 0c88 b6 62 A LDA XREG1$+1
00183 +A 0c8a b7 bc A STA TEMPXR$+1
00183 + IFC '#','#' ! immediate type 'from' address?
00183 +A 0c8c a6 00 A LDA #(.RAMSBR$)!.$FF
00183 +A 0c8e b7 62 A STA XREG1$+1 ! Set XREG1$ = 'from' address
00183 +A 0c90 a6 04 A LDA #(.RAMSBR$)!>8
00183 +A 0c92 b7 61 A STA XREG1$
00183 + ENDC
00183 + IFNC '#','#' ! not immediate type 'from' address?
00183 + ENDC
00183 + IFC '','#' ! immediate type 'to' address?
00183 + ENDC
00183 + IFNC '','#' ! not immediate type 'to' address?
00183 +A 0c94 b6 51 A LDA (LOW)+1
00183 +A 0c96 b7 66 A STA XREG2$+1 ! Set XREG2$ = 'to' address
00183 +A 0c98 b6 50 A LDA (LOW)
00183 +A 0c9a b7 65 A STA XREG2$
00183 + ENDC
00183 + IFC '#','#' ! immediate type length?
00183 + IFLE RAMSZ$-256 ! yes: 8-bit size= use X reg.
00183 +A 0c9c ae 10 A LDX #(RAMSZ$)
00183 +A 0c9e bd 60 A .00138 JSR LDAXREG
00183 +A 0ca0 bd 64 A JSR STAXREG
00183 + IFEQ XREG1$!.$FF00
00183 +A 0ca2 3c 62 A INC XREG1$+1
M6805 Portable Cross Assembler 0.05 test1.s Page 52
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00183 +A 0ca4 26 02 0ca8 BNE .00139
00183 +A 0ca6 3c 61 A INC XREG1$
00183 +A 0ca8 3c 66 A .00139 INC XREG2$+1
00183 +A 0caa 26 02 0cae BNE .00140
00183 +A 0cac 3c 65 A INC XREG2$
00183 +A 0cae 0cae A .00140 EQU *
00183 + ENDC
00183 + IFNE XREG1$!.$FF00
00183 + ENDC
00183 +A 0cae 5a DEX
00183 +A 0caf 26 ed 0c9e BNE .00138
00183 +A 0cb1 b6 bb A LDA TEMPXR$
00183 +A 0cb3 b7 61 A STA XREG1$
00183 +A 0cb5 b7 65 A STA XREG2$
00183 +A 0cb7 b6 bc A LDA TEMPXR$+1
00183 +A 0cb9 b7 62 A STA XREG1$+1
00183 +A 0cbb b7 66 A STA XREG2$+1
00183 +A 0cbd b6 b9 A LDA TEMPA$
00183 +A 0cbf be ba A LDX TEMPX$
00184 MACRO INV MOVE ,LOW,#,RAMSBR$,#,RAMSZ$ !---------
00184 + IFNE NARG-6
00184 + ENDC
00184 + IFC '#','#' ! If all immediate operands (#) and move
00184 + IFC '#','#' ! count <=256, use short form!
00184 + IFC '','#'
00184 + ENDC
00184 + ENDC
00184 + ENDC
00184 +A 0cc1 b7 b9 A STA TEMPA$
00184 +A 0cc3 bf ba A STX TEMPX$
00184 +A 0cc5 b6 61 A LDA XREG1$
00184 +A 0cc7 b7 bb A STA TEMPXR$
00184 +A 0cc9 b6 62 A LDA XREG1$+1
00184 +A 0ccb b7 bc A STA TEMPXR$+1
00184 + IFC '','#' ! immediate type 'from' address?
00184 + ENDC
00184 + IFNC '','#' ! not immediate type 'from' address?
00184 +A 0ccd b6 51 A LDA (LOW)+1
00184 +A 0ccf b7 62 A STA XREG1$+1 ! Set XREG1$ = 'from' address
00184 +A 0cd1 b6 50 A LDA (LOW)
00184 +A 0cd3 b7 61 A STA XREG1$
00184 + ENDC
00184 + IFC '#','#' ! immediate type 'to' address?
00184 +A 0cd5 a6 60 A LDA #(RAMSBR$)!.$FF
00184 +A 0cd7 b7 66 A STA XREG2$+1 ! Set XREG2$ = 'to' address
00184 +A 0cd9 a6 00 A LDA #(RAMSBR$)!>8
00184 +A 0cdb b7 65 A STA XREG2$
00184 + ENDC
00184 + IFNC '#','#' ! not immediate type 'to' address?
00184 + ENDC
00184 + IFC '#','#' ! immediate type length?
00184 + IFLE RAMSZ$-256 ! yes: 8-bit size= use X reg.
M6805 Portable Cross Assembler 0.05 test1.s Page 53
Wed May 16 10:07:20 1990
Options - MD,MC,NOG,NOU,W,MEX,CL,FMT,O
M6805 macro tests: low RAM subr's
LINE S PC OPCO OPERANDS S LABEL MNEMO OPERANDS COMMENT
00184 +A 0cdd ae 10 A LDX #(RAMSZ$)
00184 +A 0cdf bd 60 A .00141 JSR LDAXREG
00184 +A 0ce1 bd 64 A JSR STAXREG
00184 + IFEQ XREG1$!.$FF00
00184 +A 0ce3 3c 62 A INC XREG1$+1
00184 +A 0ce5 26 02 0ce9 BNE .00142
00184 +A 0ce7 3c 61 A INC XREG1$
00184 +A 0ce9 3c 66 A .00142 INC XREG2$+1
00184 +A 0ceb 26 02 0cef BNE .00143
00184 +A 0ced 3c 65 A INC XREG2$
00184 +A 0cef 0cef A .00143 EQU *
00184 + ENDC
00184 + IFNE XREG1$!.$FF00
00184 + ENDC
00184 +A 0cef 5a DEX
00184 +A 0cf0 26 ed 0cdf BNE .00141
00184 +A 0cf2 b6 bb A LDA TEMPXR$
00184 +A 0cf4 b7 61 A STA XREG1$
00184 +A 0cf6 b7 65 A STA XREG2$
00184 +A 0cf8 b6 bc A LDA TEMPXR$+1
00184 +A 0cfa b7 62 A STA XREG1$+1
00184 +A 0cfc b7 66 A STA XREG2$+1
00184 +A 0cfe b6 b9 A LDA TEMPA$
00184 +A 0d00 be ba A LDX TEMPX$
00185 END
Total number of errors: 0
Total number of warnings: 0
Total number of lines: 2345
Number of bytes in section ASCT: 2329
Number of bytes in program: 2329